nvme: add NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC
The VirtualBox emulated NVMe device will intermittently hang on the first read/write command after an I/O qpair has been allocated. The frequency of the hang diminishes if a delay is added after allocating the I/O qpair - until it disappears completely with a 100us delay. So add a quirk to insert this delay. Note - the 100us delay was tested by running the hello_world example app 50000 times. Signed-off-by: Jim Harris <james.r.harris@intel.com> Change-Id: I237e31b1b8a1a1e28262851ae0a21cd7345f0f1a
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@ -47,6 +47,7 @@ extern "C" {
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#define SPDK_PCI_ANY_ID 0xffff
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#define SPDK_PCI_ANY_ID 0xffff
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#define SPDK_PCI_VID_INTEL 0x8086
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#define SPDK_PCI_VID_INTEL 0x8086
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#define SPDK_PCI_VID_MEMBLAZE 0x1c5f
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#define SPDK_PCI_VID_MEMBLAZE 0x1c5f
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#define SPDK_PCI_VID_VIRTUALBOX 0x80ee
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/**
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/**
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* PCI class code for NVMe devices.
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* PCI class code for NVMe devices.
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@ -192,6 +192,10 @@ spdk_nvme_ctrlr_alloc_io_qpair(struct spdk_nvme_ctrlr *ctrlr,
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nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
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nvme_robust_mutex_unlock(&ctrlr->ctrlr_lock);
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if (ctrlr->quirks & NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC) {
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spdk_delay_us(100);
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}
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return qpair;
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return qpair;
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}
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}
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@ -89,6 +89,12 @@
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*/
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*/
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#define NVME_INTEL_QUIRK_STRIPING 0x8
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#define NVME_INTEL_QUIRK_STRIPING 0x8
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/*
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* The controller needs a delay after allocating an I/O queue pair
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* before it is ready to accept I/O commands.
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*/
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#define NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC 0x10
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#define NVME_MAX_ASYNC_EVENTS (8)
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#define NVME_MAX_ASYNC_EVENTS (8)
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#define NVME_MIN_TIMEOUT_PERIOD (5)
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#define NVME_MIN_TIMEOUT_PERIOD (5)
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@ -53,6 +53,9 @@ static const struct nvme_quirk nvme_quirks[] = {
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{ {SPDK_PCI_VID_MEMBLAZE, 0x0540, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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{ {SPDK_PCI_VID_MEMBLAZE, 0x0540, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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NVME_QUIRK_DELAY_BEFORE_CHK_RDY
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},
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},
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{ {SPDK_PCI_VID_VIRTUALBOX, 0x4e56, SPDK_PCI_ANY_ID, SPDK_PCI_ANY_ID},
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NVME_QUIRK_DELAY_AFTER_QUEUE_ALLOC
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},
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{ {0x0000, 0x0000, 0x0000, 0x0000}, 0}
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{ {0x0000, 0x0000, 0x0000, 0x0000}, 0}
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};
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};
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