2021-02-08 22:56:19 +00:00
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/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "spdk_cunit.h"
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#include "spdk_internal/mock.h"
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2021-06-05 12:50:15 +00:00
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#include "thread/thread_internal.h"
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2021-02-08 22:56:19 +00:00
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#include "common/lib/test_env.c"
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#include "accel/accel_engine.c"
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DEFINE_STUB(spdk_json_write_array_begin, int, (struct spdk_json_write_ctx *w), 0);
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DEFINE_STUB(spdk_json_write_array_end, int, (struct spdk_json_write_ctx *w), 0);
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2021-03-23 16:43:31 +00:00
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/* global vars and setup/cleanup functions used for all test functions */
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struct spdk_accel_engine g_accel_engine = {};
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struct spdk_io_channel *g_ch = NULL;
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struct accel_io_channel *g_accel_ch = NULL;
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2021-02-19 03:54:35 +00:00
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struct sw_accel_io_channel *g_sw_ch = NULL;
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struct spdk_io_channel *g_engine_ch = NULL;
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2021-03-23 16:43:31 +00:00
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static int
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test_setup(void)
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{
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g_ch = calloc(1, sizeof(struct spdk_io_channel) + sizeof(struct accel_io_channel));
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if (g_ch == NULL) {
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/* for some reason the assert fatal macro doesn't work in the setup function. */
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CU_ASSERT(false);
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return -1;
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}
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g_accel_ch = (struct accel_io_channel *)((char *)g_ch + sizeof(struct spdk_io_channel));
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2021-02-19 03:54:35 +00:00
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g_engine_ch = calloc(1, sizeof(struct spdk_io_channel) + sizeof(struct sw_accel_io_channel));
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if (g_engine_ch == NULL) {
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CU_ASSERT(false);
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return -1;
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}
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g_accel_ch->engine_ch = g_engine_ch;
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2021-10-14 20:53:53 +00:00
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g_accel_ch->sw_engine_ch = g_engine_ch;
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g_sw_ch = (struct sw_accel_io_channel *)((char *)g_accel_ch->sw_engine_ch + sizeof(
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2021-02-19 03:54:35 +00:00
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struct spdk_io_channel));
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TAILQ_INIT(&g_sw_ch->tasks_to_complete);
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2021-03-23 16:43:31 +00:00
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return 0;
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}
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static int
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test_cleanup(void)
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{
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free(g_ch);
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2021-02-19 03:54:35 +00:00
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free(g_engine_ch);
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2021-03-23 16:43:31 +00:00
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return 0;
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}
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2021-02-08 22:56:19 +00:00
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static void
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test_spdk_accel_hw_engine_register(void)
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{
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/* Run once with no engine assigned, assign it. */
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g_hw_accel_engine = NULL;
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2021-03-23 16:43:31 +00:00
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spdk_accel_hw_engine_register(&g_accel_engine);
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CU_ASSERT(g_hw_accel_engine == &g_accel_engine);
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2021-02-08 22:56:19 +00:00
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/* Run with one assigned, should not change. */
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2021-03-23 16:43:31 +00:00
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spdk_accel_hw_engine_register(&g_accel_engine);
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CU_ASSERT(g_hw_accel_engine == &g_accel_engine);
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2021-02-08 22:56:19 +00:00
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}
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2021-02-09 21:58:25 +00:00
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static int
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test_accel_sw_register(void)
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{
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/* Run once with no engine assigned, assign it. */
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g_sw_accel_engine = NULL;
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2021-03-23 16:43:31 +00:00
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accel_sw_register(&g_accel_engine);
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CU_ASSERT(g_sw_accel_engine == &g_accel_engine);
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2021-02-09 21:58:25 +00:00
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return 0;
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}
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static void
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test_accel_sw_unregister(void)
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{
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/* Run once engine assigned, make sure it gets unassigned. */
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2021-03-23 16:43:31 +00:00
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g_sw_accel_engine = &g_accel_engine;
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2021-02-09 21:58:25 +00:00
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accel_sw_unregister();
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CU_ASSERT(g_sw_accel_engine == NULL);
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}
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2021-02-09 22:10:29 +00:00
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static void
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test_is_supported(void)
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{
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2021-03-23 16:43:31 +00:00
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g_accel_engine.capabilities = ACCEL_COPY | ACCEL_DUALCAST | ACCEL_CRC32C;
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CU_ASSERT(_is_supported(&g_accel_engine, ACCEL_COPY) == true);
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CU_ASSERT(_is_supported(&g_accel_engine, ACCEL_FILL) == false);
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CU_ASSERT(_is_supported(&g_accel_engine, ACCEL_DUALCAST) == true);
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CU_ASSERT(_is_supported(&g_accel_engine, ACCEL_COMPARE) == false);
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CU_ASSERT(_is_supported(&g_accel_engine, ACCEL_CRC32C) == true);
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CU_ASSERT(_is_supported(&g_accel_engine, ACCEL_DIF) == false);
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2021-02-09 22:10:29 +00:00
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}
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2021-02-09 22:37:09 +00:00
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#define DUMMY_ARG 0xDEADBEEF
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static bool g_dummy_cb_called = false;
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static void
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dummy_cb_fn(void *cb_arg, int status)
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{
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CU_ASSERT(*(uint32_t *)cb_arg == DUMMY_ARG);
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CU_ASSERT(status == 0);
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g_dummy_cb_called = true;
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}
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static void
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test_spdk_accel_task_complete(void)
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{
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struct spdk_accel_task accel_task = {};
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struct spdk_accel_task *expected_accel_task = NULL;
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uint32_t cb_arg = DUMMY_ARG;
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int status = 0;
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2021-03-23 16:43:31 +00:00
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accel_task.accel_ch = g_accel_ch;
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2021-02-09 22:37:09 +00:00
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accel_task.cb_fn = dummy_cb_fn;
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accel_task.cb_arg = &cb_arg;
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2021-03-23 16:43:31 +00:00
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TAILQ_INIT(&g_accel_ch->task_pool);
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2021-02-09 22:37:09 +00:00
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2021-10-12 22:32:49 +00:00
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/* Confirm cb is called and task added to list. */
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2021-02-09 22:37:09 +00:00
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spdk_accel_task_complete(&accel_task, status);
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CU_ASSERT(g_dummy_cb_called == true);
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2021-03-23 16:43:31 +00:00
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expected_accel_task = TAILQ_FIRST(&g_accel_ch->task_pool);
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TAILQ_REMOVE(&g_accel_ch->task_pool, expected_accel_task, link);
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2021-02-09 22:37:09 +00:00
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CU_ASSERT(expected_accel_task == &accel_task);
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}
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2021-02-09 23:51:58 +00:00
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static void
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test_spdk_accel_get_capabilities(void)
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{
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uint64_t cap, expected_cap;
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2021-11-25 01:40:59 +00:00
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/* Setup a few capabilities and make sure they are reported as expected. */
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2021-03-23 16:43:31 +00:00
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g_accel_ch->engine = &g_accel_engine;
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2021-02-09 23:51:58 +00:00
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expected_cap = ACCEL_COPY | ACCEL_DUALCAST | ACCEL_CRC32C;
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2021-03-23 16:43:31 +00:00
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g_accel_ch->engine->capabilities = expected_cap;
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2021-02-09 23:51:58 +00:00
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2021-03-23 16:43:31 +00:00
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cap = spdk_accel_get_capabilities(g_ch);
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2021-02-09 23:51:58 +00:00
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CU_ASSERT(cap == expected_cap);
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}
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2021-02-10 00:00:30 +00:00
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2021-02-10 20:39:08 +00:00
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static void
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test_get_task(void)
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{
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struct spdk_accel_task *task;
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struct spdk_accel_task _task;
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void *cb_arg = NULL;
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2021-03-23 16:43:31 +00:00
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TAILQ_INIT(&g_accel_ch->task_pool);
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2021-02-10 20:39:08 +00:00
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/* no tasks left, return NULL. */
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2021-10-12 22:32:49 +00:00
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task = _get_task(g_accel_ch, dummy_cb_fn, cb_arg);
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2021-02-10 20:39:08 +00:00
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CU_ASSERT(task == NULL);
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_task.cb_fn = dummy_cb_fn;
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_task.cb_arg = cb_arg;
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2021-03-23 16:43:31 +00:00
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_task.accel_ch = g_accel_ch;
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TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &_task, link);
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2021-02-10 20:39:08 +00:00
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/* Get a valid task. */
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2021-10-12 22:32:49 +00:00
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task = _get_task(g_accel_ch, dummy_cb_fn, cb_arg);
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2021-02-10 20:39:08 +00:00
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CU_ASSERT(task == &_task);
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CU_ASSERT(_task.cb_fn == dummy_cb_fn);
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CU_ASSERT(_task.cb_arg == cb_arg);
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2021-03-23 16:43:31 +00:00
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CU_ASSERT(_task.accel_ch == g_accel_ch);
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2021-02-10 20:39:08 +00:00
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}
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2021-02-19 03:54:35 +00:00
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static bool g_dummy_submit_called = false;
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static int
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dummy_submit_tasks(struct spdk_io_channel *ch, struct spdk_accel_task *first_task)
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{
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g_dummy_submit_called = true;
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return 0;
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}
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static bool g_dummy_submit_cb_called = false;
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static void
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dummy_submit_cb_fn(void *cb_arg, int status)
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{
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g_dummy_submit_cb_called = true;
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CU_ASSERT(status == 0);
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}
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#define TEST_SUBMIT_SIZE 64
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static void
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test_spdk_accel_submit_copy(void)
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{
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const uint64_t nbytes = TEST_SUBMIT_SIZE;
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uint8_t dst[TEST_SUBMIT_SIZE];
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uint8_t src[TEST_SUBMIT_SIZE];
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void *cb_arg = NULL;
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int rc;
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struct spdk_accel_task task;
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struct spdk_accel_task *expected_accel_task = NULL;
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TAILQ_INIT(&g_accel_ch->task_pool);
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/* Fail with no tasks on _get_task() */
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rc = spdk_accel_submit_copy(g_ch, src, dst, nbytes, dummy_submit_cb_fn, cb_arg);
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CU_ASSERT(rc == -ENOMEM);
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task.cb_fn = dummy_submit_cb_fn;
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task.cb_arg = cb_arg;
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task.accel_ch = g_accel_ch;
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TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
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g_accel_ch->engine = &g_accel_engine;
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g_accel_ch->engine->capabilities = ACCEL_COPY;
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g_accel_ch->engine->submit_tasks = dummy_submit_tasks;
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/* HW accel submission OK. */
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rc = spdk_accel_submit_copy(g_ch, dst, src, nbytes, dummy_submit_cb_fn, cb_arg);
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CU_ASSERT(rc == 0);
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CU_ASSERT(task.dst == dst);
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CU_ASSERT(task.src == src);
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CU_ASSERT(task.op_code == ACCEL_OPCODE_MEMMOVE);
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CU_ASSERT(task.nbytes == nbytes);
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CU_ASSERT(g_dummy_submit_called == true);
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TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
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/* reset values before next case */
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g_dummy_submit_called = false;
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g_accel_ch->engine->capabilities = 0;
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task.dst = 0;
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task.src = 0;
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task.op_code = 0xff;
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task.nbytes = 0;
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/* SW engine does copy. */
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rc = spdk_accel_submit_copy(g_ch, dst, src, nbytes, dummy_submit_cb_fn, cb_arg);
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CU_ASSERT(rc == 0);
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CU_ASSERT(task.dst == dst);
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CU_ASSERT(task.src == src);
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CU_ASSERT(task.op_code == ACCEL_OPCODE_MEMMOVE);
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CU_ASSERT(task.nbytes == nbytes);
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CU_ASSERT(g_dummy_submit_cb_called == false);
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CU_ASSERT(memcmp(dst, src, TEST_SUBMIT_SIZE) == 0);
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expected_accel_task = TAILQ_FIRST(&g_sw_ch->tasks_to_complete);
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TAILQ_REMOVE(&g_sw_ch->tasks_to_complete, expected_accel_task, link);
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CU_ASSERT(expected_accel_task == &task);
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}
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2021-08-25 06:10:12 +00:00
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static void
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test_spdk_accel_submit_dualcast(void)
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{
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void *dst1;
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void *dst2;
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void *src;
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uint32_t align = ALIGN_4K;
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uint64_t nbytes = TEST_SUBMIT_SIZE;
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void *cb_arg = NULL;
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int rc;
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struct spdk_accel_task task;
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struct spdk_accel_task *expected_accel_task = NULL;
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/* Dualcast requires 4K alignment on dst addresses,
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* hence using the hard coded address to test the buffer alignment
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*/
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dst1 = (void *)0x5000;
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dst2 = (void *)0x60f0;
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src = calloc(1, TEST_SUBMIT_SIZE);
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SPDK_CU_ASSERT_FATAL(src != NULL);
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memset(src, 0x5A, TEST_SUBMIT_SIZE);
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TAILQ_INIT(&g_accel_ch->task_pool);
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/* This should fail since dst2 is not 4k aligned */
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rc = spdk_accel_submit_dualcast(g_ch, dst1, dst2, src, nbytes, dummy_submit_cb_fn,
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cb_arg);
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CU_ASSERT(rc == -EINVAL);
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|
|
|
|
|
|
dst1 = (void *)0x7010;
|
|
|
|
dst2 = (void *)0x6000;
|
|
|
|
/* This should fail since dst1 is not 4k aligned */
|
|
|
|
rc = spdk_accel_submit_dualcast(g_ch, dst1, dst2, src, nbytes, dummy_submit_cb_fn,
|
|
|
|
cb_arg);
|
|
|
|
CU_ASSERT(rc == -EINVAL);
|
|
|
|
|
|
|
|
/* Dualcast requires 4K alignment on dst addresses */
|
|
|
|
dst1 = (void *)0x7000;
|
|
|
|
dst2 = (void *)0x6000;
|
|
|
|
/* Fail with no tasks on _get_task() */
|
|
|
|
rc = spdk_accel_submit_dualcast(g_ch, dst1, dst2, src, nbytes, dummy_submit_cb_fn,
|
|
|
|
cb_arg);
|
|
|
|
CU_ASSERT(rc == -ENOMEM);
|
|
|
|
|
|
|
|
task.cb_fn = dummy_submit_cb_fn;
|
|
|
|
task.cb_arg = cb_arg;
|
|
|
|
task.accel_ch = g_accel_ch;
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
|
|
|
|
g_accel_ch->engine = &g_accel_engine;
|
|
|
|
g_accel_ch->engine->capabilities = ACCEL_DUALCAST;
|
|
|
|
g_accel_ch->engine->submit_tasks = dummy_submit_tasks;
|
|
|
|
|
|
|
|
/* HW accel submission OK. */
|
|
|
|
rc = spdk_accel_submit_dualcast(g_ch, dst1, dst2, src, nbytes, dummy_submit_cb_fn,
|
|
|
|
cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.dst == dst1);
|
|
|
|
CU_ASSERT(task.dst2 == dst2);
|
|
|
|
CU_ASSERT(task.src == src);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_DUALCAST);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(g_dummy_submit_called == true);
|
|
|
|
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
/* Reset values before next case */
|
|
|
|
g_dummy_submit_called = false;
|
|
|
|
g_accel_ch->engine->capabilities = 0;
|
|
|
|
task.dst = 0;
|
|
|
|
task.dst2 = 0;
|
|
|
|
task.src = 0;
|
|
|
|
task.op_code = 0xff;
|
|
|
|
task.nbytes = 0;
|
|
|
|
/* Since we test the SW path next, need to use valid memory addresses
|
|
|
|
* cannot hardcode them anymore
|
|
|
|
*/
|
|
|
|
dst1 = spdk_dma_zmalloc(nbytes, align, NULL);
|
|
|
|
SPDK_CU_ASSERT_FATAL(dst1 != NULL);
|
|
|
|
dst2 = spdk_dma_zmalloc(nbytes, align, NULL);
|
|
|
|
SPDK_CU_ASSERT_FATAL(dst2 != NULL);
|
|
|
|
/* SW engine does the dualcast. */
|
|
|
|
rc = spdk_accel_submit_dualcast(g_ch, dst1, dst2, src, nbytes, dummy_submit_cb_fn,
|
|
|
|
cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.dst == dst1);
|
|
|
|
CU_ASSERT(task.dst2 == dst2);
|
|
|
|
CU_ASSERT(task.src == src);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_DUALCAST);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(g_dummy_submit_cb_called == false);
|
|
|
|
CU_ASSERT(memcmp(dst1, src, TEST_SUBMIT_SIZE) == 0);
|
|
|
|
CU_ASSERT(memcmp(dst2, src, TEST_SUBMIT_SIZE) == 0);
|
|
|
|
expected_accel_task = TAILQ_FIRST(&g_sw_ch->tasks_to_complete);
|
|
|
|
TAILQ_REMOVE(&g_sw_ch->tasks_to_complete, expected_accel_task, link);
|
|
|
|
CU_ASSERT(expected_accel_task == &task);
|
|
|
|
|
|
|
|
free(src);
|
|
|
|
spdk_free(dst1);
|
|
|
|
spdk_free(dst2);
|
|
|
|
}
|
|
|
|
|
2021-08-25 15:26:46 +00:00
|
|
|
static void
|
|
|
|
test_spdk_accel_submit_compare(void)
|
|
|
|
{
|
|
|
|
void *src1;
|
|
|
|
void *src2;
|
|
|
|
uint64_t nbytes = TEST_SUBMIT_SIZE;
|
|
|
|
void *cb_arg = NULL;
|
|
|
|
int rc;
|
|
|
|
struct spdk_accel_task task;
|
|
|
|
struct spdk_accel_task *expected_accel_task = NULL;
|
|
|
|
|
|
|
|
src1 = calloc(1, TEST_SUBMIT_SIZE);
|
|
|
|
SPDK_CU_ASSERT_FATAL(src1 != NULL);
|
|
|
|
src2 = calloc(1, TEST_SUBMIT_SIZE);
|
|
|
|
SPDK_CU_ASSERT_FATAL(src2 != NULL);
|
|
|
|
|
|
|
|
/* Fail with no tasks on _get_task() */
|
|
|
|
rc = spdk_accel_submit_compare(g_ch, src1, src2, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == -ENOMEM);
|
|
|
|
|
|
|
|
TAILQ_INIT(&g_accel_ch->task_pool);
|
|
|
|
task.cb_fn = dummy_submit_cb_fn;
|
|
|
|
task.cb_arg = cb_arg;
|
|
|
|
task.accel_ch = g_accel_ch;
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
|
|
|
|
g_accel_ch->engine = &g_accel_engine;
|
|
|
|
g_accel_ch->engine->capabilities = ACCEL_COMPARE;
|
|
|
|
g_accel_ch->engine->submit_tasks = dummy_submit_tasks;
|
|
|
|
|
|
|
|
/* HW accel submission OK. */
|
|
|
|
rc = spdk_accel_submit_compare(g_ch, src1, src2, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.src == src1);
|
|
|
|
CU_ASSERT(task.src2 == src2);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_COMPARE);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(g_dummy_submit_called == true);
|
|
|
|
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
/* Reset values before next case */
|
|
|
|
g_dummy_submit_called = false;
|
|
|
|
g_accel_ch->engine->capabilities = 0;
|
|
|
|
task.src = 0;
|
|
|
|
task.src2 = 0;
|
|
|
|
task.op_code = 0xff;
|
|
|
|
task.nbytes = 0;
|
|
|
|
|
|
|
|
memset(src1, 0x5A, TEST_SUBMIT_SIZE);
|
|
|
|
memset(src2, 0x5A, TEST_SUBMIT_SIZE);
|
|
|
|
|
|
|
|
/* SW engine does compare. */
|
|
|
|
rc = spdk_accel_submit_compare(g_ch, src1, src2, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.src == src1);
|
|
|
|
CU_ASSERT(task.src2 == src2);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_COMPARE);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(g_dummy_submit_cb_called == false);
|
|
|
|
CU_ASSERT(memcmp(src1, src2, TEST_SUBMIT_SIZE) == 0);
|
|
|
|
expected_accel_task = TAILQ_FIRST(&g_sw_ch->tasks_to_complete);
|
|
|
|
TAILQ_REMOVE(&g_sw_ch->tasks_to_complete, expected_accel_task, link);
|
|
|
|
CU_ASSERT(expected_accel_task == &task);
|
|
|
|
|
|
|
|
free(src1);
|
|
|
|
free(src2);
|
|
|
|
}
|
|
|
|
|
2021-09-13 23:36:22 +00:00
|
|
|
static void
|
|
|
|
test_spdk_accel_submit_fill(void)
|
|
|
|
{
|
|
|
|
void *dst;
|
|
|
|
void *src;
|
|
|
|
uint8_t fill = 0xf;
|
|
|
|
uint64_t nbytes = TEST_SUBMIT_SIZE;
|
|
|
|
void *cb_arg = NULL;
|
|
|
|
int rc;
|
|
|
|
struct spdk_accel_task task;
|
|
|
|
struct spdk_accel_task *expected_accel_task = NULL;
|
|
|
|
|
|
|
|
dst = calloc(1, TEST_SUBMIT_SIZE);
|
|
|
|
SPDK_CU_ASSERT_FATAL(dst != NULL);
|
|
|
|
src = calloc(1, TEST_SUBMIT_SIZE);
|
|
|
|
SPDK_CU_ASSERT_FATAL(src != NULL);
|
|
|
|
memset(src, fill, TEST_SUBMIT_SIZE);
|
|
|
|
|
|
|
|
/* Fail with no tasks on _get_task() */
|
|
|
|
rc = spdk_accel_submit_fill(g_ch, dst, fill, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == -ENOMEM);
|
|
|
|
|
|
|
|
TAILQ_INIT(&g_accel_ch->task_pool);
|
|
|
|
task.cb_fn = dummy_submit_cb_fn;
|
|
|
|
task.cb_arg = cb_arg;
|
|
|
|
task.accel_ch = g_accel_ch;
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
|
|
|
|
g_accel_ch->engine = &g_accel_engine;
|
|
|
|
g_accel_ch->engine->capabilities = ACCEL_FILL;
|
|
|
|
g_accel_ch->engine->submit_tasks = dummy_submit_tasks;
|
|
|
|
|
|
|
|
/* HW accel submission OK. */
|
|
|
|
rc = spdk_accel_submit_fill(g_ch, dst, fill, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.dst == dst);
|
|
|
|
CU_ASSERT(task.fill_pattern == fill);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_MEMFILL);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(g_dummy_submit_called == true);
|
|
|
|
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
/* Reset values before next case */
|
|
|
|
g_dummy_submit_called = false;
|
|
|
|
g_accel_ch->engine->capabilities = 0;
|
|
|
|
task.dst = 0;
|
|
|
|
task.fill_pattern = 0;
|
|
|
|
task.op_code = 0xff;
|
|
|
|
task.nbytes = 0;
|
|
|
|
|
|
|
|
/* SW engine does the fill. */
|
|
|
|
rc = spdk_accel_submit_fill(g_ch, dst, fill, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.dst == dst);
|
|
|
|
CU_ASSERT(task.fill_pattern == fill);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_MEMFILL);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(g_dummy_submit_cb_called == false);
|
|
|
|
CU_ASSERT(memcmp(dst, src, TEST_SUBMIT_SIZE) == 0);
|
|
|
|
expected_accel_task = TAILQ_FIRST(&g_sw_ch->tasks_to_complete);
|
|
|
|
TAILQ_REMOVE(&g_sw_ch->tasks_to_complete, expected_accel_task, link);
|
|
|
|
CU_ASSERT(expected_accel_task == &task);
|
|
|
|
|
|
|
|
free(dst);
|
|
|
|
free(src);
|
|
|
|
}
|
|
|
|
|
2021-09-13 23:57:15 +00:00
|
|
|
static void
|
|
|
|
test_spdk_accel_submit_crc32c(void)
|
|
|
|
{
|
|
|
|
const uint64_t nbytes = TEST_SUBMIT_SIZE;
|
|
|
|
uint32_t crc_dst;
|
|
|
|
uint8_t src[TEST_SUBMIT_SIZE];
|
|
|
|
uint32_t seed = 1;
|
|
|
|
void *cb_arg = NULL;
|
|
|
|
int rc;
|
|
|
|
struct spdk_accel_task task;
|
|
|
|
struct spdk_accel_task *expected_accel_task = NULL;
|
|
|
|
|
|
|
|
/* Fail with no tasks on _get_task() */
|
|
|
|
rc = spdk_accel_submit_crc32c(g_ch, &crc_dst, src, seed, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == -ENOMEM);
|
|
|
|
|
|
|
|
TAILQ_INIT(&g_accel_ch->task_pool);
|
|
|
|
task.cb_fn = dummy_submit_cb_fn;
|
|
|
|
task.cb_arg = cb_arg;
|
|
|
|
task.accel_ch = g_accel_ch;
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
|
|
|
|
g_accel_ch->engine = &g_accel_engine;
|
|
|
|
g_accel_ch->engine->capabilities = ACCEL_CRC32C;
|
|
|
|
g_accel_ch->engine->submit_tasks = dummy_submit_tasks;
|
|
|
|
|
|
|
|
/* HW accel submission OK. */
|
|
|
|
rc = spdk_accel_submit_crc32c(g_ch, &crc_dst, src, seed, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.crc_dst == &crc_dst);
|
|
|
|
CU_ASSERT(task.src == src);
|
|
|
|
CU_ASSERT(task.v.iovcnt == 0);
|
|
|
|
CU_ASSERT(task.seed == seed);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_CRC32C);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(g_dummy_submit_called == true);
|
|
|
|
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
/* Reset values before next case */
|
|
|
|
g_dummy_submit_called = false;
|
|
|
|
g_accel_ch->engine->capabilities = 0;
|
|
|
|
task.crc_dst = 0;
|
|
|
|
task.src = 0;
|
|
|
|
task.seed = 0;
|
|
|
|
task.op_code = 0xff;
|
|
|
|
task.nbytes = 0;
|
|
|
|
|
|
|
|
/* SW engine does crc. */
|
|
|
|
rc = spdk_accel_submit_crc32c(g_ch, &crc_dst, src, seed, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.crc_dst == &crc_dst);
|
|
|
|
CU_ASSERT(task.src == src);
|
|
|
|
CU_ASSERT(task.v.iovcnt == 0);
|
|
|
|
CU_ASSERT(task.seed == seed);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_CRC32C);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(g_dummy_submit_cb_called == false);
|
|
|
|
expected_accel_task = TAILQ_FIRST(&g_sw_ch->tasks_to_complete);
|
|
|
|
TAILQ_REMOVE(&g_sw_ch->tasks_to_complete, expected_accel_task, link);
|
|
|
|
CU_ASSERT(expected_accel_task == &task);
|
|
|
|
}
|
|
|
|
|
2021-10-14 20:53:53 +00:00
|
|
|
static void
|
|
|
|
test_spdk_accel_submit_crc32c_hw_engine_unsupported(void)
|
|
|
|
{
|
|
|
|
const uint64_t nbytes = TEST_SUBMIT_SIZE;
|
|
|
|
uint32_t crc_dst;
|
|
|
|
uint8_t src[TEST_SUBMIT_SIZE];
|
|
|
|
uint32_t seed = 1;
|
|
|
|
void *cb_arg = NULL;
|
|
|
|
int rc;
|
|
|
|
struct spdk_accel_task task;
|
|
|
|
struct spdk_accel_task *expected_accel_task = NULL;
|
|
|
|
|
|
|
|
/* Fail with no tasks on _get_task() */
|
|
|
|
rc = spdk_accel_submit_crc32c(g_ch, &crc_dst, src, seed, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == -ENOMEM);
|
|
|
|
|
|
|
|
TAILQ_INIT(&g_accel_ch->task_pool);
|
|
|
|
task.cb_fn = dummy_submit_cb_fn;
|
|
|
|
task.cb_arg = cb_arg;
|
|
|
|
task.accel_ch = g_accel_ch;
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
|
|
|
|
g_accel_ch->engine = &g_accel_engine;
|
|
|
|
/* HW engine only supports COPY and does not support CRC */
|
|
|
|
g_accel_ch->engine->capabilities = ACCEL_COPY;
|
|
|
|
g_accel_ch->engine->submit_tasks = dummy_submit_tasks;
|
|
|
|
|
|
|
|
/* Summit to HW engine while eventually handled by SW engine. */
|
|
|
|
rc = spdk_accel_submit_crc32c(g_ch, &crc_dst, src, seed, nbytes, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.crc_dst == &crc_dst);
|
|
|
|
CU_ASSERT(task.src == src);
|
|
|
|
CU_ASSERT(task.v.iovcnt == 0);
|
|
|
|
CU_ASSERT(task.seed == seed);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_CRC32C);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
/* Not set in HW engine callback while handled by SW engine instead. */
|
|
|
|
CU_ASSERT(g_dummy_submit_called == false);
|
|
|
|
|
|
|
|
/* SW engine does crc. */
|
|
|
|
expected_accel_task = TAILQ_FIRST(&g_sw_ch->tasks_to_complete);
|
|
|
|
TAILQ_REMOVE(&g_sw_ch->tasks_to_complete, expected_accel_task, link);
|
|
|
|
CU_ASSERT(expected_accel_task == &task);
|
|
|
|
}
|
|
|
|
|
2021-09-14 22:06:47 +00:00
|
|
|
static void
|
|
|
|
test_spdk_accel_submit_crc32cv(void)
|
|
|
|
{
|
|
|
|
uint32_t crc_dst;
|
|
|
|
uint32_t seed = 0;
|
|
|
|
uint32_t iov_cnt = 32;
|
|
|
|
void *cb_arg = NULL;
|
|
|
|
int rc;
|
|
|
|
uint32_t i = 0;
|
|
|
|
struct spdk_accel_task task;
|
|
|
|
struct iovec iov[32];
|
|
|
|
struct spdk_accel_task *expected_accel_task = NULL;
|
|
|
|
|
|
|
|
for (i = 0; i < iov_cnt; i++) {
|
|
|
|
iov[i].iov_base = calloc(1, TEST_SUBMIT_SIZE);
|
|
|
|
SPDK_CU_ASSERT_FATAL(iov[i].iov_base != NULL);
|
|
|
|
iov[i].iov_len = TEST_SUBMIT_SIZE;
|
|
|
|
}
|
|
|
|
|
|
|
|
TAILQ_INIT(&g_accel_ch->task_pool);
|
|
|
|
task.cb_fn = dummy_submit_cb_fn;
|
|
|
|
task.cb_arg = cb_arg;
|
|
|
|
task.accel_ch = g_accel_ch;
|
|
|
|
task.nbytes = TEST_SUBMIT_SIZE;
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
|
|
|
|
g_accel_ch->engine = &g_accel_engine;
|
|
|
|
g_accel_ch->engine->capabilities = ACCEL_CRC32C;
|
|
|
|
g_accel_ch->engine->submit_tasks = dummy_submit_tasks;
|
|
|
|
|
|
|
|
/* HW accel submission OK. */
|
|
|
|
rc = spdk_accel_submit_crc32cv(g_ch, &crc_dst, iov, iov_cnt, seed, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.v.iovs == iov);
|
|
|
|
CU_ASSERT(task.v.iovcnt == iov_cnt);
|
|
|
|
CU_ASSERT(task.crc_dst == &crc_dst);
|
|
|
|
CU_ASSERT(task.seed == seed);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_CRC32C);
|
|
|
|
CU_ASSERT(g_dummy_submit_called == true);
|
2021-11-17 18:48:24 +00:00
|
|
|
CU_ASSERT(task.cb_fn == dummy_submit_cb_fn);
|
|
|
|
CU_ASSERT(task.cb_arg == cb_arg);
|
2021-09-14 22:06:47 +00:00
|
|
|
CU_ASSERT(task.nbytes == iov[0].iov_len);
|
|
|
|
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
g_dummy_submit_called = false;
|
|
|
|
g_accel_ch->engine->capabilities = 0;
|
|
|
|
task.v.iovs = 0;
|
|
|
|
task.v.iovcnt = 0;
|
|
|
|
task.crc_dst = 0;
|
|
|
|
task.seed = 0;
|
|
|
|
task.op_code = 0xff;
|
|
|
|
|
|
|
|
/* SW engine submit crc. */
|
|
|
|
rc = spdk_accel_submit_crc32cv(g_ch, &crc_dst, iov, iov_cnt, seed, dummy_submit_cb_fn, cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.v.iovs == iov);
|
|
|
|
CU_ASSERT(task.v.iovcnt == iov_cnt);
|
|
|
|
CU_ASSERT(task.crc_dst == &crc_dst);
|
|
|
|
CU_ASSERT(task.seed == seed);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_CRC32C);
|
|
|
|
CU_ASSERT(g_dummy_submit_cb_called == false);
|
|
|
|
|
|
|
|
expected_accel_task = TAILQ_FIRST(&g_sw_ch->tasks_to_complete);
|
|
|
|
TAILQ_REMOVE(&g_sw_ch->tasks_to_complete, expected_accel_task, link);
|
|
|
|
CU_ASSERT(expected_accel_task == &task);
|
|
|
|
|
|
|
|
for (i = 0; i < iov_cnt; i++) {
|
|
|
|
free(iov[i].iov_base);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-09-14 22:24:37 +00:00
|
|
|
static void
|
|
|
|
test_spdk_accel_submit_copy_crc32c(void)
|
|
|
|
{
|
|
|
|
const uint64_t nbytes = TEST_SUBMIT_SIZE;
|
|
|
|
uint32_t crc_dst;
|
|
|
|
uint8_t dst[TEST_SUBMIT_SIZE];
|
|
|
|
uint8_t src[TEST_SUBMIT_SIZE];
|
|
|
|
uint32_t seed = 0;
|
|
|
|
void *cb_arg = NULL;
|
|
|
|
int rc;
|
|
|
|
struct spdk_accel_task task;
|
|
|
|
struct spdk_accel_task *expected_accel_task = NULL;
|
|
|
|
|
|
|
|
/* Fail with no tasks on _get_task() */
|
|
|
|
rc = spdk_accel_submit_copy_crc32c(g_ch, dst, src, &crc_dst, seed, nbytes, dummy_submit_cb_fn,
|
|
|
|
cb_arg);
|
|
|
|
CU_ASSERT(rc == -ENOMEM);
|
|
|
|
|
|
|
|
TAILQ_INIT(&g_accel_ch->task_pool);
|
|
|
|
task.cb_fn = dummy_submit_cb_fn;
|
|
|
|
task.cb_arg = cb_arg;
|
|
|
|
task.accel_ch = g_accel_ch;
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
|
|
|
|
g_accel_ch->engine = &g_accel_engine;
|
|
|
|
g_accel_ch->engine->capabilities = ACCEL_COPY_CRC32C;
|
|
|
|
g_accel_ch->engine->submit_tasks = dummy_submit_tasks;
|
|
|
|
|
|
|
|
/* HW accel submission OK. */
|
|
|
|
rc = spdk_accel_submit_copy_crc32c(g_ch, dst, src, &crc_dst, seed, nbytes, dummy_submit_cb_fn,
|
|
|
|
cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(task.dst == dst);
|
|
|
|
CU_ASSERT(task.src == src);
|
|
|
|
CU_ASSERT(task.crc_dst == &crc_dst);
|
|
|
|
CU_ASSERT(task.v.iovcnt == 0);
|
|
|
|
CU_ASSERT(task.seed == seed);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_COPY_CRC32C);
|
|
|
|
CU_ASSERT(g_dummy_submit_called == true);
|
|
|
|
|
|
|
|
TAILQ_INSERT_TAIL(&g_accel_ch->task_pool, &task, link);
|
|
|
|
g_dummy_submit_called = false;
|
|
|
|
task.dst = 0;
|
|
|
|
task.src = 0;
|
|
|
|
task.crc_dst = 0;
|
|
|
|
task.v.iovcnt = 0;
|
|
|
|
task.seed = 0;
|
|
|
|
task.nbytes = 0;
|
|
|
|
task.op_code = 0xff;
|
|
|
|
g_accel_ch->engine->capabilities = 0;
|
|
|
|
memset(src, 0x5A, TEST_SUBMIT_SIZE);
|
|
|
|
|
|
|
|
/* SW engine does copy crc. */
|
|
|
|
rc = spdk_accel_submit_copy_crc32c(g_ch, dst, src, &crc_dst, seed, nbytes, dummy_submit_cb_fn,
|
|
|
|
cb_arg);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(memcmp(dst, src, TEST_SUBMIT_SIZE) == 0);
|
|
|
|
CU_ASSERT(task.dst == dst);
|
|
|
|
CU_ASSERT(task.src == src);
|
|
|
|
CU_ASSERT(task.crc_dst == &crc_dst);
|
|
|
|
CU_ASSERT(task.v.iovcnt == 0);
|
|
|
|
CU_ASSERT(task.seed == seed);
|
|
|
|
CU_ASSERT(task.nbytes == nbytes);
|
|
|
|
CU_ASSERT(task.op_code == ACCEL_OPCODE_COPY_CRC32C);
|
|
|
|
CU_ASSERT(g_dummy_submit_cb_called == false);
|
|
|
|
expected_accel_task = TAILQ_FIRST(&g_sw_ch->tasks_to_complete);
|
|
|
|
TAILQ_REMOVE(&g_sw_ch->tasks_to_complete, expected_accel_task, link);
|
|
|
|
CU_ASSERT(expected_accel_task == &task);
|
|
|
|
}
|
|
|
|
|
2021-02-08 22:56:19 +00:00
|
|
|
int main(int argc, char **argv)
|
|
|
|
{
|
|
|
|
CU_pSuite suite = NULL;
|
|
|
|
unsigned int num_failures;
|
|
|
|
|
|
|
|
CU_set_error_action(CUEA_ABORT);
|
|
|
|
CU_initialize_registry();
|
|
|
|
|
2021-03-23 16:43:31 +00:00
|
|
|
suite = CU_add_suite("accel", test_setup, test_cleanup);
|
2021-02-08 22:56:19 +00:00
|
|
|
|
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_hw_engine_register);
|
2021-02-09 21:58:25 +00:00
|
|
|
CU_ADD_TEST(suite, test_accel_sw_register);
|
|
|
|
CU_ADD_TEST(suite, test_accel_sw_unregister);
|
2021-02-09 22:10:29 +00:00
|
|
|
CU_ADD_TEST(suite, test_is_supported);
|
2021-02-09 22:37:09 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_task_complete);
|
2021-02-09 23:51:58 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_get_capabilities);
|
2021-02-10 20:39:08 +00:00
|
|
|
CU_ADD_TEST(suite, test_get_task);
|
2021-02-19 03:54:35 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_submit_copy);
|
2021-08-25 06:10:12 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_submit_dualcast);
|
2021-08-25 15:26:46 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_submit_compare);
|
2021-09-13 23:36:22 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_submit_fill);
|
2021-09-13 23:57:15 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_submit_crc32c);
|
2021-10-14 20:53:53 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_submit_crc32c_hw_engine_unsupported);
|
2021-09-14 22:06:47 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_submit_crc32cv);
|
2021-09-14 22:24:37 +00:00
|
|
|
CU_ADD_TEST(suite, test_spdk_accel_submit_copy_crc32c);
|
2021-02-08 22:56:19 +00:00
|
|
|
|
|
|
|
CU_basic_set_mode(CU_BRM_VERBOSE);
|
|
|
|
CU_basic_run_tests();
|
|
|
|
num_failures = CU_get_number_of_failures();
|
|
|
|
CU_cleanup_registry();
|
|
|
|
|
|
|
|
return num_failures;
|
|
|
|
}
|