2022-08-05 19:54:16 +00:00
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/* SPDX-License-Identifier: BSD-3-Clause
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2022-11-01 20:26:26 +00:00
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* Copyright (C) 2022 Intel Corporation.
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2022-08-05 19:54:16 +00:00
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* All rights reserved.
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*/
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#include "spdk/stdinc.h"
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2022-08-08 21:43:24 +00:00
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#include "spdk_internal/accel_module.h"
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2022-08-05 19:54:16 +00:00
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#include "spdk/env.h"
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#include "spdk/likely.h"
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#include "spdk/log.h"
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#include "spdk/thread.h"
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#include "spdk/json.h"
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#include "spdk/crc32.h"
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#include "spdk/util.h"
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#ifdef SPDK_CONFIG_PMDK
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#include "libpmem.h"
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#endif
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#ifdef SPDK_CONFIG_ISAL
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#include "../isa-l/include/igzip_lib.h"
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#endif
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struct sw_accel_io_channel {
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/* for ISAL */
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#ifdef SPDK_CONFIG_ISAL
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struct isal_zstream stream;
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struct inflate_state state;
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#endif
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struct spdk_poller *completion_poller;
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TAILQ_HEAD(, spdk_accel_task) tasks_to_complete;
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};
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/* Post SW completions to a list and complete in a poller as we don't want to
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* complete them on the caller's stack as they'll likely submit another. */
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inline static void
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_add_to_comp_list(struct sw_accel_io_channel *sw_ch, struct spdk_accel_task *accel_task, int status)
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{
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accel_task->status = status;
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TAILQ_INSERT_TAIL(&sw_ch->tasks_to_complete, accel_task, link);
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}
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/* Used when the SW engine is selected and the durable flag is set. */
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inline static int
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_check_flags(int flags)
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{
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if (flags & ACCEL_FLAG_PERSISTENT) {
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#ifndef SPDK_CONFIG_PMDK
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/* PMDK is required to use this flag. */
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SPDK_ERRLOG("ACCEL_FLAG_PERSISTENT set but PMDK not configured. Configure PMDK or do not use this flag.\n");
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return -EINVAL;
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#endif
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}
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return 0;
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}
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static bool
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sw_accel_supports_opcode(enum accel_opcode opc)
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{
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switch (opc) {
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case ACCEL_OPC_COPY:
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case ACCEL_OPC_FILL:
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case ACCEL_OPC_DUALCAST:
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case ACCEL_OPC_COMPARE:
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case ACCEL_OPC_CRC32C:
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case ACCEL_OPC_COPY_CRC32C:
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case ACCEL_OPC_COMPRESS:
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case ACCEL_OPC_DECOMPRESS:
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return true;
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default:
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return false;
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}
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}
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static inline void
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_pmem_memcpy(void *dst, const void *src, size_t len)
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{
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#ifdef SPDK_CONFIG_PMDK
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int is_pmem = pmem_is_pmem(dst, len);
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if (is_pmem) {
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pmem_memcpy_persist(dst, src, len);
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} else {
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memcpy(dst, src, len);
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pmem_msync(dst, len);
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}
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#else
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SPDK_ERRLOG("Function not defined without SPDK_CONFIG_PMDK enabled.\n");
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assert(0);
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#endif
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}
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static void
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_sw_accel_dualcast(void *dst1, void *dst2, void *src, size_t nbytes, int flags)
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{
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if (flags & ACCEL_FLAG_PERSISTENT) {
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_pmem_memcpy(dst1, src, nbytes);
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_pmem_memcpy(dst2, src, nbytes);
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} else {
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memcpy(dst1, src, nbytes);
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memcpy(dst2, src, nbytes);
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}
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}
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static void
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_sw_accel_copy(void *dst, void *src, size_t nbytes, int flags)
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{
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if (flags & ACCEL_FLAG_PERSISTENT) {
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_pmem_memcpy(dst, src, nbytes);
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} else {
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memcpy(dst, src, nbytes);
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}
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}
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static void
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_sw_accel_copyv(void *dst, struct iovec *iov, uint32_t iovcnt, int flags)
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{
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uint32_t i;
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for (i = 0; i < iovcnt; i++) {
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assert(iov[i].iov_base != NULL);
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if (flags & ACCEL_FLAG_PERSISTENT) {
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_pmem_memcpy(dst, iov[i].iov_base, (size_t)iov[i].iov_len);
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} else {
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memcpy(dst, iov[i].iov_base, (size_t)iov[i].iov_len);
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}
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dst += iov[i].iov_len;
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}
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}
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static int
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_sw_accel_compare(void *src1, void *src2, size_t nbytes)
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{
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return memcmp(src1, src2, nbytes);
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}
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static void
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_sw_accel_fill(void *dst, uint8_t fill, size_t nbytes, int flags)
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{
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if (flags & ACCEL_FLAG_PERSISTENT) {
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#ifdef SPDK_CONFIG_PMDK
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int is_pmem = pmem_is_pmem(dst, nbytes);
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if (is_pmem) {
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pmem_memset_persist(dst, fill, nbytes);
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} else {
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memset(dst, fill, nbytes);
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pmem_msync(dst, nbytes);
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}
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#else
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SPDK_ERRLOG("Function not defined without SPDK_CONFIG_PMDK enabled.\n");
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assert(0);
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#endif
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} else {
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memset(dst, fill, nbytes);
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}
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}
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static void
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_sw_accel_crc32c(uint32_t *crc_dst, void *src, uint32_t seed, uint64_t nbytes)
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{
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*crc_dst = spdk_crc32c_update(src, nbytes, ~seed);
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}
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static void
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_sw_accel_crc32cv(uint32_t *crc_dst, struct iovec *iov, uint32_t iovcnt, uint32_t seed)
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{
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*crc_dst = spdk_crc32c_iov_update(iov, iovcnt, ~seed);
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}
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static int
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_sw_accel_compress(struct sw_accel_io_channel *sw_ch, struct spdk_accel_task *accel_task)
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{
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#ifdef SPDK_CONFIG_ISAL
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2022-09-22 19:01:56 +00:00
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size_t last_seglen = accel_task->s.iovs[accel_task->s.iovcnt - 1].iov_len;
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struct iovec *siov = accel_task->s.iovs;
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struct iovec *diov = accel_task->d.iovs;
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size_t remaining = accel_task->nbytes;
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uint32_t s = 0, d = 0;
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int rc = 0;
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accel_task->d.iovcnt = 1;
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diov[0].iov_base = accel_task->dst;
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diov[0].iov_len = accel_task->nbytes_dst;
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isal_deflate_reset(&sw_ch->stream);
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sw_ch->stream.end_of_stream = 0;
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sw_ch->stream.next_out = diov[d].iov_base;
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sw_ch->stream.avail_out = diov[d].iov_len;
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sw_ch->stream.next_in = siov[s].iov_base;
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sw_ch->stream.avail_in = siov[s].iov_len;
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do {
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/* if isal has exhausted the current dst iovec, move to the next
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* one if there is one */
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if (sw_ch->stream.avail_out == 0) {
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if (++d < accel_task->d.iovcnt) {
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sw_ch->stream.next_out = diov[d].iov_base;
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sw_ch->stream.avail_out = diov[d].iov_len;
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assert(sw_ch->stream.avail_out > 0);
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} else {
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/* we have no avail_out but also no more iovecs left so this is
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2022-10-05 20:15:58 +00:00
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* the case where either the output buffer was a perfect fit
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* or not enough was provided. Check the ISAL state to determine
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* which. */
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if (sw_ch->stream.internal_state.state != ZSTATE_END) {
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SPDK_ERRLOG("Not enough destination buffer provided.\n");
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rc = -ENOMEM;
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}
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2022-09-22 19:01:56 +00:00
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break;
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}
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}
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2022-08-05 19:54:16 +00:00
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2022-09-22 19:01:56 +00:00
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/* if isal has exhausted the current src iovec, move to the next
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* one if there is one */
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if (sw_ch->stream.avail_in == 0 && ((s + 1) < accel_task->s.iovcnt)) {
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s++;
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sw_ch->stream.next_in = siov[s].iov_base;
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sw_ch->stream.avail_in = siov[s].iov_len;
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assert(sw_ch->stream.avail_in > 0);
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}
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if (remaining <= last_seglen) {
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/* Need to set end of stream on last block */
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sw_ch->stream.end_of_stream = 1;
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}
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rc = isal_deflate(&sw_ch->stream);
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if (rc) {
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SPDK_ERRLOG("isal_deflate retunred error %d.\n", rc);
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}
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if (remaining > 0) {
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assert(siov[s].iov_len > sw_ch->stream.avail_in);
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remaining -= (siov[s].iov_len - sw_ch->stream.avail_in);
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}
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} while (remaining > 0 || sw_ch->stream.avail_out == 0);
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assert(sw_ch->stream.avail_in == 0);
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/* Get our total output size */
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2022-08-05 19:54:16 +00:00
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if (accel_task->output_size != NULL) {
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2022-09-22 19:01:56 +00:00
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assert(sw_ch->stream.total_out > 0);
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*accel_task->output_size = sw_ch->stream.total_out;
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2022-08-05 19:54:16 +00:00
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}
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2022-09-22 19:01:56 +00:00
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return rc;
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2022-08-05 19:54:16 +00:00
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#else
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SPDK_ERRLOG("ISAL option is required to use software compression.\n");
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return -EINVAL;
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#endif
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}
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static int
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_sw_accel_decompress(struct sw_accel_io_channel *sw_ch, struct spdk_accel_task *accel_task)
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{
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#ifdef SPDK_CONFIG_ISAL
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2022-09-22 19:01:56 +00:00
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struct iovec *siov = accel_task->s.iovs;
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struct iovec *diov = accel_task->d.iovs;
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uint32_t s = 0, d = 0;
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int rc = 0;
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2022-08-05 19:54:16 +00:00
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2022-09-22 19:01:56 +00:00
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isal_inflate_reset(&sw_ch->state);
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sw_ch->state.next_out = diov[d].iov_base;
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sw_ch->state.avail_out = diov[d].iov_len;
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sw_ch->state.next_in = siov[s].iov_base;
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sw_ch->state.avail_in = siov[s].iov_len;
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do {
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/* if isal has exhausted the current dst iovec, move to the next
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* one if there is one */
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if (sw_ch->state.avail_out == 0 && ((d + 1) < accel_task->d.iovcnt)) {
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d++;
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sw_ch->state.next_out = diov[d].iov_base;
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sw_ch->state.avail_out = diov[d].iov_len;
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assert(sw_ch->state.avail_out > 0);
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}
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/* if isal has exhausted the current src iovec, move to the next
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* one if there is one */
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if (sw_ch->state.avail_in == 0 && ((s + 1) < accel_task->s.iovcnt)) {
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s++;
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sw_ch->state.next_in = siov[s].iov_base;
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sw_ch->state.avail_in = siov[s].iov_len;
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assert(sw_ch->state.avail_in > 0);
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}
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rc = isal_inflate(&sw_ch->state);
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if (rc) {
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SPDK_ERRLOG("isal_inflate retunred error %d.\n", rc);
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}
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} while (sw_ch->state.block_state < ISAL_BLOCK_FINISH);
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assert(sw_ch->state.avail_in == 0);
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2022-08-05 19:54:16 +00:00
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return rc;
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#else
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SPDK_ERRLOG("ISAL option is required to use software decompression.\n");
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return -EINVAL;
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#endif
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}
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static int
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sw_accel_submit_tasks(struct spdk_io_channel *ch, struct spdk_accel_task *accel_task)
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{
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struct sw_accel_io_channel *sw_ch = spdk_io_channel_get_ctx(ch);
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struct spdk_accel_task *tmp;
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int rc = 0;
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do {
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switch (accel_task->op_code) {
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case ACCEL_OPC_COPY:
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rc = _check_flags(accel_task->flags);
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if (rc == 0) {
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_sw_accel_copy(accel_task->dst, accel_task->src, accel_task->nbytes, accel_task->flags);
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}
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break;
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case ACCEL_OPC_FILL:
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rc = _check_flags(accel_task->flags);
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if (rc == 0) {
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_sw_accel_fill(accel_task->dst, accel_task->fill_pattern, accel_task->nbytes, accel_task->flags);
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}
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break;
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case ACCEL_OPC_DUALCAST:
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rc = _check_flags(accel_task->flags);
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if (rc == 0) {
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_sw_accel_dualcast(accel_task->dst, accel_task->dst2, accel_task->src, accel_task->nbytes,
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accel_task->flags);
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}
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break;
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case ACCEL_OPC_COMPARE:
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rc = _sw_accel_compare(accel_task->src, accel_task->src2, accel_task->nbytes);
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break;
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case ACCEL_OPC_CRC32C:
|
2022-07-21 21:57:11 +00:00
|
|
|
if (accel_task->s.iovcnt == 0) {
|
2022-08-05 19:54:16 +00:00
|
|
|
_sw_accel_crc32c(accel_task->crc_dst, accel_task->src, accel_task->seed, accel_task->nbytes);
|
|
|
|
} else {
|
2022-07-21 21:57:11 +00:00
|
|
|
_sw_accel_crc32cv(accel_task->crc_dst, accel_task->s.iovs, accel_task->s.iovcnt, accel_task->seed);
|
2022-08-05 19:54:16 +00:00
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ACCEL_OPC_COPY_CRC32C:
|
|
|
|
rc = _check_flags(accel_task->flags);
|
|
|
|
if (rc == 0) {
|
2022-07-21 21:57:11 +00:00
|
|
|
if (accel_task->s.iovcnt == 0) {
|
2022-08-05 19:54:16 +00:00
|
|
|
_sw_accel_copy(accel_task->dst, accel_task->src, accel_task->nbytes, accel_task->flags);
|
|
|
|
_sw_accel_crc32c(accel_task->crc_dst, accel_task->src, accel_task->seed, accel_task->nbytes);
|
|
|
|
} else {
|
2022-07-21 21:57:11 +00:00
|
|
|
_sw_accel_copyv(accel_task->dst, accel_task->s.iovs, accel_task->s.iovcnt, accel_task->flags);
|
|
|
|
_sw_accel_crc32cv(accel_task->crc_dst, accel_task->s.iovs, accel_task->s.iovcnt, accel_task->seed);
|
2022-08-05 19:54:16 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
case ACCEL_OPC_COMPRESS:
|
|
|
|
rc = _sw_accel_compress(sw_ch, accel_task);
|
|
|
|
break;
|
|
|
|
case ACCEL_OPC_DECOMPRESS:
|
|
|
|
rc = _sw_accel_decompress(sw_ch, accel_task);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(false);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
tmp = TAILQ_NEXT(accel_task, link);
|
|
|
|
|
|
|
|
_add_to_comp_list(sw_ch, accel_task, rc);
|
|
|
|
|
|
|
|
accel_task = tmp;
|
|
|
|
} while (accel_task);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct spdk_io_channel *sw_accel_get_io_channel(void);
|
2022-08-08 21:43:24 +00:00
|
|
|
static int sw_accel_module_init(void);
|
|
|
|
static void sw_accel_module_fini(void *ctxt);
|
|
|
|
static size_t sw_accel_module_get_ctx_size(void);
|
2022-08-05 19:54:16 +00:00
|
|
|
|
|
|
|
static struct spdk_accel_module_if g_sw_module = {
|
2022-08-08 21:43:24 +00:00
|
|
|
.module_init = sw_accel_module_init,
|
|
|
|
.module_fini = sw_accel_module_fini,
|
2022-08-05 19:54:16 +00:00
|
|
|
.write_config_json = NULL,
|
2022-08-08 21:43:24 +00:00
|
|
|
.get_ctx_size = sw_accel_module_get_ctx_size,
|
2022-08-05 19:54:16 +00:00
|
|
|
.name = "software",
|
|
|
|
.supports_opcode = sw_accel_supports_opcode,
|
|
|
|
.get_io_channel = sw_accel_get_io_channel,
|
|
|
|
.submit_tasks = sw_accel_submit_tasks
|
|
|
|
};
|
|
|
|
|
|
|
|
static int
|
|
|
|
accel_comp_poll(void *arg)
|
|
|
|
{
|
|
|
|
struct sw_accel_io_channel *sw_ch = arg;
|
|
|
|
TAILQ_HEAD(, spdk_accel_task) tasks_to_complete;
|
|
|
|
struct spdk_accel_task *accel_task;
|
|
|
|
|
|
|
|
if (TAILQ_EMPTY(&sw_ch->tasks_to_complete)) {
|
|
|
|
return SPDK_POLLER_IDLE;
|
|
|
|
}
|
|
|
|
|
|
|
|
TAILQ_INIT(&tasks_to_complete);
|
|
|
|
TAILQ_SWAP(&tasks_to_complete, &sw_ch->tasks_to_complete, spdk_accel_task, link);
|
|
|
|
|
|
|
|
while ((accel_task = TAILQ_FIRST(&tasks_to_complete))) {
|
|
|
|
TAILQ_REMOVE(&tasks_to_complete, accel_task, link);
|
|
|
|
spdk_accel_task_complete(accel_task, accel_task->status);
|
|
|
|
}
|
|
|
|
|
|
|
|
return SPDK_POLLER_BUSY;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
sw_accel_create_cb(void *io_device, void *ctx_buf)
|
|
|
|
{
|
|
|
|
struct sw_accel_io_channel *sw_ch = ctx_buf;
|
|
|
|
|
|
|
|
TAILQ_INIT(&sw_ch->tasks_to_complete);
|
|
|
|
sw_ch->completion_poller = SPDK_POLLER_REGISTER(accel_comp_poll, sw_ch, 0);
|
|
|
|
|
|
|
|
#ifdef SPDK_CONFIG_ISAL
|
2022-09-22 19:01:56 +00:00
|
|
|
isal_deflate_init(&sw_ch->stream);
|
|
|
|
sw_ch->stream.flush = NO_FLUSH;
|
2022-08-05 19:54:16 +00:00
|
|
|
sw_ch->stream.level = 1;
|
|
|
|
sw_ch->stream.level_buf = calloc(1, ISAL_DEF_LVL1_DEFAULT);
|
|
|
|
if (sw_ch->stream.level_buf == NULL) {
|
|
|
|
SPDK_ERRLOG("Could not allocate isal internal buffer\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
sw_ch->stream.level_buf_size = ISAL_DEF_LVL1_DEFAULT;
|
|
|
|
isal_inflate_init(&sw_ch->state);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
sw_accel_destroy_cb(void *io_device, void *ctx_buf)
|
|
|
|
{
|
|
|
|
struct sw_accel_io_channel *sw_ch = ctx_buf;
|
|
|
|
|
|
|
|
#ifdef SPDK_CONFIG_ISAL
|
|
|
|
free(sw_ch->stream.level_buf);
|
|
|
|
#endif
|
|
|
|
|
|
|
|
spdk_poller_unregister(&sw_ch->completion_poller);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct spdk_io_channel *
|
|
|
|
sw_accel_get_io_channel(void)
|
|
|
|
{
|
|
|
|
return spdk_get_io_channel(&g_sw_module);
|
|
|
|
}
|
|
|
|
|
|
|
|
static size_t
|
2022-08-08 21:43:24 +00:00
|
|
|
sw_accel_module_get_ctx_size(void)
|
2022-08-05 19:54:16 +00:00
|
|
|
{
|
|
|
|
return sizeof(struct spdk_accel_task);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2022-08-08 21:43:24 +00:00
|
|
|
sw_accel_module_init(void)
|
2022-08-05 19:54:16 +00:00
|
|
|
{
|
2022-08-08 21:43:24 +00:00
|
|
|
SPDK_NOTICELOG("Accel framework software module initialized.\n");
|
2022-08-05 19:54:16 +00:00
|
|
|
spdk_io_device_register(&g_sw_module, sw_accel_create_cb, sw_accel_destroy_cb,
|
2022-08-08 21:43:24 +00:00
|
|
|
sizeof(struct sw_accel_io_channel), "sw_accel_module");
|
2022-08-05 19:54:16 +00:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
2022-08-08 21:43:24 +00:00
|
|
|
sw_accel_module_fini(void *ctxt)
|
2022-08-05 19:54:16 +00:00
|
|
|
{
|
|
|
|
spdk_io_device_unregister(&g_sw_module, NULL);
|
2022-08-08 20:36:34 +00:00
|
|
|
spdk_accel_module_finish();
|
2022-08-05 19:54:16 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
SPDK_ACCEL_MODULE_REGISTER(sw, &g_sw_module)
|