2018-10-03 21:02:54 +00:00
|
|
|
/*-
|
|
|
|
* BSD LICENSE
|
|
|
|
*
|
|
|
|
* Copyright (c) Intel Corporation.
|
|
|
|
* All rights reserved.
|
|
|
|
*
|
|
|
|
* Redistribution and use in source and binary forms, with or without
|
|
|
|
* modification, are permitted provided that the following conditions
|
|
|
|
* are met:
|
|
|
|
*
|
|
|
|
* * Redistributions of source code must retain the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer.
|
|
|
|
* * Redistributions in binary form must reproduce the above copyright
|
|
|
|
* notice, this list of conditions and the following disclaimer in
|
|
|
|
* the documentation and/or other materials provided with the
|
|
|
|
* distribution.
|
|
|
|
* * Neither the name of Intel Corporation nor the names of its
|
|
|
|
* contributors may be used to endorse or promote products derived
|
|
|
|
* from this software without specific prior written permission.
|
|
|
|
*
|
|
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include "spdk/stdinc.h"
|
|
|
|
#include "spdk_cunit.h"
|
|
|
|
#include "nvme/nvme_rdma.c"
|
2020-01-07 21:18:38 +00:00
|
|
|
#include "common/lib/nvme/common_stubs.h"
|
2020-03-14 09:20:44 +00:00
|
|
|
#include "common/lib/test_rdma.c"
|
2018-10-03 21:02:54 +00:00
|
|
|
|
2020-09-04 11:27:29 +00:00
|
|
|
SPDK_LOG_REGISTER_COMPONENT(nvme)
|
2018-10-03 21:02:54 +00:00
|
|
|
|
|
|
|
DEFINE_STUB(spdk_mem_map_set_translation, int, (struct spdk_mem_map *map, uint64_t vaddr,
|
|
|
|
uint64_t size, uint64_t translation), 0);
|
|
|
|
DEFINE_STUB(spdk_mem_map_clear_translation, int, (struct spdk_mem_map *map, uint64_t vaddr,
|
|
|
|
uint64_t size), 0);
|
|
|
|
|
2019-12-26 17:10:02 +00:00
|
|
|
DEFINE_STUB(spdk_mem_map_alloc, struct spdk_mem_map *, (uint64_t default_translation,
|
|
|
|
const struct spdk_mem_map_ops *ops, void *cb_ctx), NULL);
|
|
|
|
DEFINE_STUB_V(spdk_mem_map_free, (struct spdk_mem_map **pmap));
|
|
|
|
|
2020-03-05 21:47:49 +00:00
|
|
|
DEFINE_STUB(nvme_poll_group_connect_qpair, int, (struct spdk_nvme_qpair *qpair), 0);
|
|
|
|
|
|
|
|
DEFINE_STUB_V(nvme_qpair_resubmit_requests, (struct spdk_nvme_qpair *qpair, uint32_t num_requests));
|
|
|
|
DEFINE_STUB(spdk_nvme_poll_group_process_completions, int64_t, (struct spdk_nvme_poll_group *group,
|
|
|
|
uint32_t completions_per_qpair, spdk_nvme_disconnected_qpair_cb disconnected_qpair_cb), 0)
|
|
|
|
|
2018-10-03 21:02:54 +00:00
|
|
|
struct nvme_rdma_ut_bdev_io {
|
|
|
|
struct iovec iovs[NVME_RDMA_MAX_SGL_DESCRIPTORS];
|
|
|
|
int iovpos;
|
|
|
|
};
|
|
|
|
|
|
|
|
/* essentially a simplification of bdev_nvme_next_sge and bdev_nvme_reset_sgl */
|
|
|
|
static void nvme_rdma_ut_reset_sgl(void *cb_arg, uint32_t offset)
|
|
|
|
{
|
|
|
|
struct nvme_rdma_ut_bdev_io *bio = cb_arg;
|
|
|
|
struct iovec *iov;
|
|
|
|
|
|
|
|
for (bio->iovpos = 0; bio->iovpos < NVME_RDMA_MAX_SGL_DESCRIPTORS; bio->iovpos++) {
|
|
|
|
iov = &bio->iovs[bio->iovpos];
|
|
|
|
/* Only provide offsets at the beginning of an iov */
|
|
|
|
if (offset == 0) {
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset -= iov->iov_len;
|
|
|
|
}
|
|
|
|
|
|
|
|
SPDK_CU_ASSERT_FATAL(bio->iovpos < NVME_RDMA_MAX_SGL_DESCRIPTORS);
|
|
|
|
}
|
|
|
|
|
|
|
|
static int nvme_rdma_ut_next_sge(void *cb_arg, void **address, uint32_t *length)
|
|
|
|
{
|
|
|
|
struct nvme_rdma_ut_bdev_io *bio = cb_arg;
|
|
|
|
struct iovec *iov;
|
|
|
|
|
|
|
|
SPDK_CU_ASSERT_FATAL(bio->iovpos < NVME_RDMA_MAX_SGL_DESCRIPTORS);
|
|
|
|
|
|
|
|
iov = &bio->iovs[bio->iovpos];
|
|
|
|
|
|
|
|
*address = iov->iov_base;
|
|
|
|
*length = iov->iov_len;
|
|
|
|
bio->iovpos++;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
test_nvme_rdma_build_sgl_request(void)
|
|
|
|
{
|
|
|
|
struct nvme_rdma_qpair rqpair;
|
|
|
|
struct spdk_nvme_ctrlr ctrlr = {0};
|
|
|
|
struct spdk_nvmf_cmd cmd = {{0}};
|
|
|
|
struct spdk_nvme_rdma_req rdma_req = {0};
|
|
|
|
struct nvme_request req = {{0}};
|
|
|
|
struct nvme_rdma_ut_bdev_io bio;
|
|
|
|
uint64_t i;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
ctrlr.max_sges = NVME_RDMA_MAX_SGL_DESCRIPTORS;
|
2018-10-11 23:21:05 +00:00
|
|
|
ctrlr.cdata.nvmf_specific.msdbd = 16;
|
2020-09-09 13:19:39 +00:00
|
|
|
ctrlr.ioccsz_bytes = 4096;
|
2018-10-03 21:02:54 +00:00
|
|
|
|
2020-11-10 17:37:41 +00:00
|
|
|
rqpair.mr_map = (struct spdk_rdma_mem_map *)0xdeadbeef;
|
|
|
|
rqpair.rdma_qp = (struct spdk_rdma_qp *)0xdeadbeef;
|
2018-10-03 21:02:54 +00:00
|
|
|
rqpair.qpair.ctrlr = &ctrlr;
|
|
|
|
rqpair.cmds = &cmd;
|
|
|
|
cmd.sgl[0].address = 0x1111;
|
|
|
|
rdma_req.id = 0;
|
|
|
|
rdma_req.req = &req;
|
|
|
|
|
|
|
|
req.payload.reset_sgl_fn = nvme_rdma_ut_reset_sgl;
|
|
|
|
req.payload.next_sge_fn = nvme_rdma_ut_next_sge;
|
|
|
|
req.payload.contig_or_cb_arg = &bio;
|
|
|
|
req.qpair = &rqpair.qpair;
|
|
|
|
|
|
|
|
for (i = 0; i < NVME_RDMA_MAX_SGL_DESCRIPTORS; i++) {
|
|
|
|
bio.iovs[i].iov_base = (void *)i;
|
|
|
|
bio.iovs[i].iov_len = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Test case 1: single SGL. Expected: PASS */
|
|
|
|
bio.iovpos = 0;
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 0x1000;
|
|
|
|
bio.iovs[0].iov_len = 0x1000;
|
|
|
|
rc = nvme_rdma_build_sgl_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == 0);
|
|
|
|
CU_ASSERT(bio.iovpos == 1);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.keyed.type == SPDK_NVME_SGL_TYPE_KEYED_DATA_BLOCK);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.keyed.subtype == SPDK_NVME_SGL_SUBTYPE_ADDRESS);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.keyed.length == req.payload_size);
|
2020-11-10 17:37:41 +00:00
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.keyed.key == RDMA_UT_RKEY);
|
2018-10-03 21:02:54 +00:00
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == (uint64_t)bio.iovs[0].iov_base);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[0].length == sizeof(struct spdk_nvme_cmd));
|
|
|
|
|
|
|
|
/* Test case 2: multiple SGL. Expected: PASS */
|
|
|
|
bio.iovpos = 0;
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 0x4000;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
bio.iovs[i].iov_len = 0x1000;
|
|
|
|
}
|
|
|
|
rc = nvme_rdma_build_sgl_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == 0);
|
|
|
|
CU_ASSERT(bio.iovpos == 4);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.type == SPDK_NVME_SGL_TYPE_LAST_SEGMENT);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.subtype == SPDK_NVME_SGL_SUBTYPE_OFFSET);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.length == 4 * sizeof(struct spdk_nvme_sgl_descriptor));
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == (uint64_t)0);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[0].length == 4 * sizeof(struct spdk_nvme_sgl_descriptor) + sizeof(
|
|
|
|
struct spdk_nvme_cmd))
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
CU_ASSERT(cmd.sgl[i].keyed.type == SPDK_NVME_SGL_TYPE_KEYED_DATA_BLOCK);
|
|
|
|
CU_ASSERT(cmd.sgl[i].keyed.subtype == SPDK_NVME_SGL_SUBTYPE_ADDRESS);
|
|
|
|
CU_ASSERT(cmd.sgl[i].keyed.length == bio.iovs[i].iov_len);
|
2020-11-10 17:37:41 +00:00
|
|
|
CU_ASSERT(cmd.sgl[i].keyed.key == RDMA_UT_RKEY);
|
2018-10-03 21:02:54 +00:00
|
|
|
CU_ASSERT(cmd.sgl[i].address == (uint64_t)bio.iovs[i].iov_base);
|
|
|
|
}
|
|
|
|
|
2018-10-11 23:21:05 +00:00
|
|
|
/* Test case 3: Multiple SGL, SGL 2X mr size. Expected: FAIL */
|
2018-10-03 21:02:54 +00:00
|
|
|
bio.iovpos = 0;
|
|
|
|
req.payload_offset = 0;
|
2018-10-11 23:21:05 +00:00
|
|
|
g_mr_size = 0x800;
|
2018-10-03 21:02:54 +00:00
|
|
|
rc = nvme_rdma_build_sgl_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc != 0);
|
|
|
|
CU_ASSERT(bio.iovpos == 1);
|
|
|
|
|
2020-06-25 12:19:49 +00:00
|
|
|
/* Test case 4: Multiple SGL, SGL size smaller than I/O size. Expected: FAIL */
|
2018-10-03 21:02:54 +00:00
|
|
|
bio.iovpos = 0;
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 0x6000;
|
|
|
|
g_mr_size = 0x0;
|
|
|
|
rc = nvme_rdma_build_sgl_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc != 0);
|
|
|
|
CU_ASSERT(bio.iovpos == NVME_RDMA_MAX_SGL_DESCRIPTORS);
|
2020-06-25 12:19:49 +00:00
|
|
|
|
|
|
|
/* Test case 5: SGL length exceeds 3 bytes. Expected: FAIL */
|
|
|
|
req.payload_size = 0x1000 + (1 << 24);
|
|
|
|
bio.iovs[0].iov_len = 0x1000;
|
|
|
|
bio.iovs[1].iov_len = 1 << 24;
|
|
|
|
rc = nvme_rdma_build_sgl_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc != 0);
|
2020-09-09 13:19:39 +00:00
|
|
|
|
|
|
|
/* Test case 6: 4 SGL descriptors, size of SGL descriptors exceeds ICD. Expected: FAIL */
|
|
|
|
ctrlr.ioccsz_bytes = 60;
|
|
|
|
bio.iovpos = 0;
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 0x4000;
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
bio.iovs[i].iov_len = 0x1000;
|
|
|
|
}
|
|
|
|
rc = nvme_rdma_build_sgl_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == -1);
|
2020-06-25 12:19:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
test_nvme_rdma_build_sgl_inline_request(void)
|
|
|
|
{
|
|
|
|
struct nvme_rdma_qpair rqpair;
|
|
|
|
struct spdk_nvme_ctrlr ctrlr = {0};
|
|
|
|
struct spdk_nvmf_cmd cmd = {{0}};
|
|
|
|
struct spdk_nvme_rdma_req rdma_req = {0};
|
|
|
|
struct nvme_request req = {{0}};
|
|
|
|
struct nvme_rdma_ut_bdev_io bio;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
ctrlr.max_sges = NVME_RDMA_MAX_SGL_DESCRIPTORS;
|
|
|
|
ctrlr.cdata.nvmf_specific.msdbd = 16;
|
|
|
|
|
2020-11-10 17:37:41 +00:00
|
|
|
rqpair.mr_map = (struct spdk_rdma_mem_map *)0xdeadbeef;
|
|
|
|
rqpair.rdma_qp = (struct spdk_rdma_qp *)0xdeadbeef;
|
2020-06-25 12:19:49 +00:00
|
|
|
rqpair.qpair.ctrlr = &ctrlr;
|
|
|
|
rqpair.cmds = &cmd;
|
|
|
|
cmd.sgl[0].address = 0x1111;
|
|
|
|
rdma_req.id = 0;
|
|
|
|
rdma_req.req = &req;
|
|
|
|
|
|
|
|
req.payload.reset_sgl_fn = nvme_rdma_ut_reset_sgl;
|
|
|
|
req.payload.next_sge_fn = nvme_rdma_ut_next_sge;
|
|
|
|
req.payload.contig_or_cb_arg = &bio;
|
|
|
|
req.qpair = &rqpair.qpair;
|
|
|
|
|
|
|
|
/* Test case 1: single inline SGL. Expected: PASS */
|
|
|
|
bio.iovpos = 0;
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 0x1000;
|
|
|
|
bio.iovs[0].iov_base = (void *)0xdeadbeef;
|
|
|
|
bio.iovs[0].iov_len = 0x1000;
|
|
|
|
rc = nvme_rdma_build_sgl_inline_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == 0);
|
|
|
|
CU_ASSERT(bio.iovpos == 1);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.type == SPDK_NVME_SGL_TYPE_DATA_BLOCK);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.subtype == SPDK_NVME_SGL_SUBTYPE_OFFSET);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.length == req.payload_size);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == 0);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[0].length == sizeof(struct spdk_nvme_cmd));
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].length == req.payload_size);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].addr == (uint64_t)bio.iovs[0].iov_base);
|
2020-11-10 17:37:41 +00:00
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].lkey == RDMA_UT_LKEY);
|
2020-06-25 12:19:49 +00:00
|
|
|
|
|
|
|
/* Test case 2: SGL length exceeds 3 bytes. Expected: PASS */
|
|
|
|
bio.iovpos = 0;
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 1 << 24;
|
|
|
|
bio.iovs[0].iov_len = 1 << 24;
|
|
|
|
rc = nvme_rdma_build_sgl_inline_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == 0);
|
|
|
|
CU_ASSERT(bio.iovpos == 1);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.type == SPDK_NVME_SGL_TYPE_DATA_BLOCK);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.subtype == SPDK_NVME_SGL_SUBTYPE_OFFSET);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.length == req.payload_size);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == 0);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[0].length == sizeof(struct spdk_nvme_cmd));
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].length == req.payload_size);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].addr == (uint64_t)bio.iovs[0].iov_base);
|
2020-11-10 17:37:41 +00:00
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].lkey == RDMA_UT_LKEY);
|
2020-06-25 12:19:49 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
test_nvme_rdma_build_contig_request(void)
|
|
|
|
{
|
|
|
|
struct nvme_rdma_qpair rqpair;
|
|
|
|
struct spdk_nvme_ctrlr ctrlr = {0};
|
|
|
|
struct spdk_nvmf_cmd cmd = {{0}};
|
|
|
|
struct spdk_nvme_rdma_req rdma_req = {0};
|
|
|
|
struct nvme_request req = {{0}};
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
ctrlr.max_sges = NVME_RDMA_MAX_SGL_DESCRIPTORS;
|
|
|
|
ctrlr.cdata.nvmf_specific.msdbd = 16;
|
|
|
|
|
2020-11-10 17:37:41 +00:00
|
|
|
rqpair.mr_map = (struct spdk_rdma_mem_map *)0xdeadbeef;
|
|
|
|
rqpair.rdma_qp = (struct spdk_rdma_qp *)0xdeadbeef;
|
2020-06-25 12:19:49 +00:00
|
|
|
rqpair.qpair.ctrlr = &ctrlr;
|
|
|
|
rqpair.cmds = &cmd;
|
|
|
|
cmd.sgl[0].address = 0x1111;
|
|
|
|
rdma_req.id = 0;
|
|
|
|
rdma_req.req = &req;
|
|
|
|
|
|
|
|
req.payload.contig_or_cb_arg = (void *)0xdeadbeef;
|
|
|
|
req.qpair = &rqpair.qpair;
|
|
|
|
|
|
|
|
/* Test case 1: contig request. Expected: PASS */
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 0x1000;
|
|
|
|
rc = nvme_rdma_build_contig_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == 0);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.keyed.type == SPDK_NVME_SGL_TYPE_KEYED_DATA_BLOCK);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.keyed.subtype == SPDK_NVME_SGL_SUBTYPE_ADDRESS);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.keyed.length == req.payload_size);
|
2020-11-10 17:37:41 +00:00
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.keyed.key == RDMA_UT_RKEY);
|
2020-06-25 12:19:49 +00:00
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == (uint64_t)req.payload.contig_or_cb_arg);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[0].length == sizeof(struct spdk_nvme_cmd));
|
|
|
|
|
|
|
|
/* Test case 2: SGL length exceeds 3 bytes. Expected: FAIL */
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 1 << 24;
|
|
|
|
rc = nvme_rdma_build_contig_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc != 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
test_nvme_rdma_build_contig_inline_request(void)
|
|
|
|
{
|
|
|
|
struct nvme_rdma_qpair rqpair;
|
|
|
|
struct spdk_nvme_ctrlr ctrlr = {0};
|
|
|
|
struct spdk_nvmf_cmd cmd = {{0}};
|
|
|
|
struct spdk_nvme_rdma_req rdma_req = {0};
|
|
|
|
struct nvme_request req = {{0}};
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
ctrlr.max_sges = NVME_RDMA_MAX_SGL_DESCRIPTORS;
|
|
|
|
ctrlr.cdata.nvmf_specific.msdbd = 16;
|
|
|
|
|
2020-11-10 17:37:41 +00:00
|
|
|
rqpair.mr_map = (struct spdk_rdma_mem_map *)0xdeadbeef;
|
|
|
|
rqpair.rdma_qp = (struct spdk_rdma_qp *)0xdeadbeef;
|
2020-06-25 12:19:49 +00:00
|
|
|
rqpair.qpair.ctrlr = &ctrlr;
|
|
|
|
rqpair.cmds = &cmd;
|
|
|
|
cmd.sgl[0].address = 0x1111;
|
|
|
|
rdma_req.id = 0;
|
|
|
|
rdma_req.req = &req;
|
|
|
|
|
|
|
|
req.payload.contig_or_cb_arg = (void *)0xdeadbeef;
|
|
|
|
req.qpair = &rqpair.qpair;
|
|
|
|
|
|
|
|
/* Test case 1: single inline SGL. Expected: PASS */
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 0x1000;
|
|
|
|
rc = nvme_rdma_build_contig_inline_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == 0);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.type == SPDK_NVME_SGL_TYPE_DATA_BLOCK);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.subtype == SPDK_NVME_SGL_SUBTYPE_OFFSET);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.length == req.payload_size);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == 0);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[0].length == sizeof(struct spdk_nvme_cmd));
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].length == req.payload_size);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].addr == (uint64_t)req.payload.contig_or_cb_arg);
|
2020-11-10 17:37:41 +00:00
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].lkey == RDMA_UT_LKEY);
|
2020-06-25 12:19:49 +00:00
|
|
|
|
|
|
|
/* Test case 2: SGL length exceeds 3 bytes. Expected: PASS */
|
|
|
|
req.payload_offset = 0;
|
|
|
|
req.payload_size = 1 << 24;
|
|
|
|
rc = nvme_rdma_build_contig_inline_request(&rqpair, &rdma_req);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == 0);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.type == SPDK_NVME_SGL_TYPE_DATA_BLOCK);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.subtype == SPDK_NVME_SGL_SUBTYPE_OFFSET);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.length == req.payload_size);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == 0);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[0].length == sizeof(struct spdk_nvme_cmd));
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].length == req.payload_size);
|
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].addr == (uint64_t)req.payload.contig_or_cb_arg);
|
2020-11-10 17:37:41 +00:00
|
|
|
CU_ASSERT(rdma_req.send_sgl[1].lkey == RDMA_UT_LKEY);
|
2018-10-03 21:02:54 +00:00
|
|
|
}
|
|
|
|
|
2021-01-15 06:03:58 +00:00
|
|
|
static void
|
|
|
|
test_nvme_rdma_alloc_reqs(void)
|
|
|
|
{
|
2021-02-05 17:46:16 +00:00
|
|
|
struct nvme_rdma_qpair rqpair = {};
|
2021-01-15 06:03:58 +00:00
|
|
|
int rc;
|
|
|
|
|
|
|
|
memset(&g_nvme_hooks, 0, sizeof(g_nvme_hooks));
|
|
|
|
|
|
|
|
/* Test case 1: zero entry. Expect: FAIL */
|
|
|
|
rqpair.num_entries = 0;
|
|
|
|
|
|
|
|
rc = nvme_rdma_alloc_reqs(&rqpair);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs == NULL);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == -ENOMEM);
|
|
|
|
|
|
|
|
/* Test case 2: single entry. Expect: PASS */
|
|
|
|
memset(&rqpair, 0, sizeof(rqpair));
|
|
|
|
rqpair.num_entries = 1;
|
|
|
|
|
|
|
|
rc = nvme_rdma_alloc_reqs(&rqpair);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[0].send_sgl[0].addr
|
|
|
|
== (uint64_t)&rqpair.cmds[0]);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[0].send_wr.wr_id
|
|
|
|
== (uint64_t)&rqpair.rdma_reqs[0].rdma_wr);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[0].send_wr.next == NULL);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[0].send_wr.opcode == IBV_WR_SEND);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[0].send_wr.send_flags == IBV_SEND_SIGNALED);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[0].send_wr.sg_list
|
|
|
|
== rqpair.rdma_reqs[0].send_sgl);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[0].send_wr.imm_data == 0);
|
|
|
|
spdk_free(rqpair.rdma_reqs);
|
|
|
|
spdk_free(rqpair.cmds);
|
|
|
|
|
|
|
|
/* Test case 3: multiple entries. Expect: PASS */
|
|
|
|
memset(&rqpair, 0, sizeof(rqpair));
|
|
|
|
rqpair.num_entries = 5;
|
|
|
|
|
|
|
|
rc = nvme_rdma_alloc_reqs(&rqpair);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
for (int i = 0; i < 5; i++) {
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[i].send_sgl[0].addr
|
|
|
|
== (uint64_t)&rqpair.cmds[i]);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[i].send_wr.wr_id
|
|
|
|
== (uint64_t)&rqpair.rdma_reqs[i].rdma_wr);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[i].send_wr.next == NULL);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[i].send_wr.opcode == IBV_WR_SEND);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[i].send_wr.send_flags
|
|
|
|
== IBV_SEND_SIGNALED);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[i].send_wr.sg_list
|
|
|
|
== rqpair.rdma_reqs[i].send_sgl);
|
|
|
|
CU_ASSERT(rqpair.rdma_reqs[i].send_wr.imm_data == 0);
|
|
|
|
}
|
|
|
|
spdk_free(rqpair.rdma_reqs);
|
|
|
|
spdk_free(rqpair.cmds);
|
|
|
|
}
|
|
|
|
|
2021-01-28 01:00:12 +00:00
|
|
|
static void
|
|
|
|
test_nvme_rdma_alloc_rsps(void)
|
|
|
|
{
|
|
|
|
struct nvme_rdma_qpair rqpair = {0};
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
memset(&g_nvme_hooks, 0, sizeof(g_nvme_hooks));
|
|
|
|
|
|
|
|
/* Test case 1 calloc false */
|
|
|
|
rqpair.num_entries = 0;
|
|
|
|
rc = nvme_rdma_alloc_rsps(&rqpair);
|
|
|
|
CU_ASSERT(rqpair.rsp_sgls == NULL);
|
|
|
|
SPDK_CU_ASSERT_FATAL(rc == -ENOMEM);
|
|
|
|
|
|
|
|
/* Test case 2 calloc success */
|
|
|
|
memset(&rqpair, 0, sizeof(rqpair));
|
|
|
|
rqpair.num_entries = 1;
|
|
|
|
|
|
|
|
rc = nvme_rdma_alloc_rsps(&rqpair);
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(rqpair.rsp_sgls != NULL);
|
|
|
|
CU_ASSERT(rqpair.rsp_recv_wrs != NULL);
|
|
|
|
CU_ASSERT(rqpair.rsps != NULL);
|
|
|
|
nvme_rdma_free_rsps(&rqpair);
|
|
|
|
}
|
|
|
|
|
2021-02-19 02:02:48 +00:00
|
|
|
static void
|
|
|
|
test_nvme_rdma_ctrlr_create_qpair(void)
|
|
|
|
{
|
|
|
|
struct spdk_nvme_ctrlr ctrlr = {};
|
|
|
|
uint16_t qid, qsize;
|
|
|
|
struct spdk_nvme_qpair *qpair;
|
|
|
|
struct nvme_rdma_qpair *rqpair;
|
|
|
|
|
|
|
|
/* Test case 1: max qsize. Expect: PASS */
|
|
|
|
qsize = 0xffff;
|
|
|
|
qid = 1;
|
|
|
|
|
|
|
|
qpair = nvme_rdma_ctrlr_create_qpair(&ctrlr, qid, qsize,
|
|
|
|
SPDK_NVME_QPRIO_URGENT, 1,
|
|
|
|
false);
|
|
|
|
CU_ASSERT(qpair != NULL);
|
|
|
|
rqpair = SPDK_CONTAINEROF(qpair, struct nvme_rdma_qpair, qpair);
|
|
|
|
CU_ASSERT(qpair == &rqpair->qpair);
|
|
|
|
CU_ASSERT(rqpair->num_entries == qsize);
|
|
|
|
CU_ASSERT(rqpair->delay_cmd_submit == false);
|
|
|
|
CU_ASSERT(rqpair->rsp_sgls != NULL);
|
|
|
|
CU_ASSERT(rqpair->rsp_recv_wrs != NULL);
|
|
|
|
CU_ASSERT(rqpair->rsps != NULL);
|
|
|
|
|
|
|
|
nvme_rdma_free_reqs(rqpair);
|
|
|
|
nvme_rdma_free_rsps(rqpair);
|
|
|
|
nvme_rdma_free(rqpair);
|
|
|
|
rqpair = NULL;
|
|
|
|
|
|
|
|
/* Test case 2: queue qsize zero. ExpectL FAIL */
|
|
|
|
qsize = 0;
|
|
|
|
|
|
|
|
qpair = nvme_rdma_ctrlr_create_qpair(&ctrlr, qid, qsize,
|
|
|
|
SPDK_NVME_QPRIO_URGENT, 1,
|
|
|
|
false);
|
|
|
|
SPDK_CU_ASSERT_FATAL(qpair == NULL);
|
|
|
|
}
|
|
|
|
|
2021-02-26 02:15:01 +00:00
|
|
|
DEFINE_STUB(ibv_create_cq, struct ibv_cq *, (struct ibv_context *context, int cqe, void *cq_context,
|
|
|
|
struct ibv_comp_channel *channel, int comp_vector), (struct ibv_cq *)0xFEEDBEEF);
|
|
|
|
DEFINE_STUB(ibv_destroy_cq, int, (struct ibv_cq *cq), 0);
|
|
|
|
|
|
|
|
static void
|
|
|
|
test_nvme_rdma_poller_create(void)
|
|
|
|
{
|
|
|
|
struct nvme_rdma_poll_group group = {};
|
|
|
|
struct ibv_context *contexts = (struct ibv_context *)0xDEADBEEF;
|
|
|
|
|
|
|
|
/* Case: calloc and ibv not need to fail test */
|
|
|
|
STAILQ_INIT(&group.pollers);
|
|
|
|
group.num_pollers = 1;
|
|
|
|
int rc = nvme_rdma_poller_create(&group, contexts);
|
|
|
|
|
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(group.num_pollers = 2);
|
|
|
|
CU_ASSERT(&group.pollers != NULL);
|
|
|
|
CU_ASSERT(group.pollers.stqh_first->device == contexts);
|
|
|
|
CU_ASSERT(group.pollers.stqh_first->cq == (struct ibv_cq *)0xFEEDBEEF);
|
|
|
|
CU_ASSERT(group.pollers.stqh_first->current_num_wc == DEFAULT_NVME_RDMA_CQ_SIZE);
|
|
|
|
CU_ASSERT(group.pollers.stqh_first->required_num_wc == 0);
|
|
|
|
|
|
|
|
nvme_rdma_poll_group_free_pollers(&group);
|
|
|
|
}
|
|
|
|
|
2018-10-03 21:02:54 +00:00
|
|
|
int main(int argc, char **argv)
|
|
|
|
{
|
|
|
|
CU_pSuite suite = NULL;
|
|
|
|
unsigned int num_failures;
|
|
|
|
|
2020-03-11 17:59:24 +00:00
|
|
|
CU_set_error_action(CUEA_ABORT);
|
|
|
|
CU_initialize_registry();
|
2018-10-03 21:02:54 +00:00
|
|
|
|
|
|
|
suite = CU_add_suite("nvme_rdma", NULL, NULL);
|
2020-03-11 19:15:39 +00:00
|
|
|
CU_ADD_TEST(suite, test_nvme_rdma_build_sgl_request);
|
2020-06-25 12:19:49 +00:00
|
|
|
CU_ADD_TEST(suite, test_nvme_rdma_build_sgl_inline_request);
|
|
|
|
CU_ADD_TEST(suite, test_nvme_rdma_build_contig_request);
|
|
|
|
CU_ADD_TEST(suite, test_nvme_rdma_build_contig_inline_request);
|
2021-01-15 06:03:58 +00:00
|
|
|
CU_ADD_TEST(suite, test_nvme_rdma_alloc_reqs);
|
2021-01-28 01:00:12 +00:00
|
|
|
CU_ADD_TEST(suite, test_nvme_rdma_alloc_rsps);
|
2021-02-19 02:02:48 +00:00
|
|
|
CU_ADD_TEST(suite, test_nvme_rdma_ctrlr_create_qpair);
|
2021-02-26 02:15:01 +00:00
|
|
|
CU_ADD_TEST(suite, test_nvme_rdma_poller_create);
|
2018-10-03 21:02:54 +00:00
|
|
|
|
|
|
|
CU_basic_set_mode(CU_BRM_VERBOSE);
|
|
|
|
CU_basic_run_tests();
|
|
|
|
num_failures = CU_get_number_of_failures();
|
|
|
|
CU_cleanup_registry();
|
|
|
|
return num_failures;
|
|
|
|
}
|