2020-04-07 16:38:58 +00:00
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/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "accel_engine_idxd.h"
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#include "spdk/stdinc.h"
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#include "spdk_internal/accel_engine.h"
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#include "spdk_internal/log.h"
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#include "spdk_internal/idxd.h"
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#include "spdk/env.h"
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#include "spdk/conf.h"
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#include "spdk/event.h"
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#include "spdk/thread.h"
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#include "spdk/idxd.h"
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#include "spdk/util.h"
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2020-04-27 15:45:46 +00:00
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#include "spdk/json.h"
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2020-04-07 16:38:58 +00:00
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2020-06-16 17:24:35 +00:00
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#define ALIGN_4K 0x1000
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2020-04-07 16:38:58 +00:00
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static bool g_idxd_enable = false;
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2020-04-27 15:45:46 +00:00
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uint32_t g_config_number;
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2020-04-07 16:38:58 +00:00
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enum channel_state {
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IDXD_CHANNEL_ACTIVE,
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IDXD_CHANNEL_PAUSED,
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IDXD_CHANNEL_ERROR,
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};
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static bool g_idxd_initialized = false;
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struct pci_device {
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struct spdk_pci_device *pci_dev;
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TAILQ_ENTRY(pci_device) tailq;
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};
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static TAILQ_HEAD(, pci_device) g_pci_devices = TAILQ_HEAD_INITIALIZER(g_pci_devices);
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struct idxd_device {
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struct spdk_idxd_device *idxd;
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int num_channels;
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TAILQ_ENTRY(idxd_device) tailq;
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};
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static TAILQ_HEAD(, idxd_device) g_idxd_devices = TAILQ_HEAD_INITIALIZER(g_idxd_devices);
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static struct idxd_device *g_next_dev = NULL;
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struct idxd_op {
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struct spdk_idxd_io_channel *chan;
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void *cb_arg;
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spdk_idxd_req_cb cb_fn;
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void *src;
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2020-04-29 22:56:11 +00:00
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union {
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void *dst;
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void *src2;
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};
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2020-04-30 22:07:58 +00:00
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void *dst2;
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2020-04-29 17:36:30 +00:00
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uint32_t seed;
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2020-04-07 16:38:58 +00:00
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uint64_t fill_pattern;
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uint32_t op_code;
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uint64_t nbytes;
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2020-05-07 18:45:15 +00:00
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struct idxd_batch *batch;
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2020-04-07 16:38:58 +00:00
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TAILQ_ENTRY(idxd_op) link;
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};
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struct idxd_io_channel {
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struct spdk_idxd_io_channel *chan;
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struct spdk_idxd_device *idxd;
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struct idxd_device *dev;
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enum channel_state state;
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struct spdk_poller *poller;
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TAILQ_HEAD(, idxd_op) queued_ops;
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};
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struct idxd_task {
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spdk_accel_completion_cb cb;
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};
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2020-07-02 14:45:28 +00:00
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pthread_mutex_t g_configuration_lock = PTHREAD_MUTEX_INITIALIZER;
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2020-04-07 16:38:58 +00:00
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2020-04-24 16:47:55 +00:00
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static struct spdk_io_channel *idxd_get_io_channel(void);
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2020-04-07 16:38:58 +00:00
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static struct idxd_device *
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idxd_select_device(void)
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{
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/*
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* We allow channels to share underlying devices,
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* selection is round-robin based.
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*/
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2020-05-07 18:45:15 +00:00
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2020-04-07 16:38:58 +00:00
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g_next_dev = TAILQ_NEXT(g_next_dev, tailq);
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if (g_next_dev == NULL) {
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g_next_dev = TAILQ_FIRST(&g_idxd_devices);
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}
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return g_next_dev;
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}
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static int
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idxd_poll(void *arg)
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{
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struct idxd_io_channel *chan = arg;
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struct idxd_op *op = NULL;
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int rc;
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spdk_idxd_process_events(chan->chan);
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/* Check if there are any pending ops to process if the channel is active */
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if (chan->state != IDXD_CHANNEL_ACTIVE) {
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return -1;
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}
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while (!TAILQ_EMPTY(&chan->queued_ops)) {
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op = TAILQ_FIRST(&chan->queued_ops);
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switch (op->op_code) {
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case IDXD_OPCODE_MEMMOVE:
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rc = spdk_idxd_submit_copy(op->chan, op->dst, op->src, op->nbytes,
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op->cb_fn, op->cb_arg);
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break;
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2020-04-30 22:07:58 +00:00
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case IDXD_OPCODE_DUALCAST:
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rc = spdk_idxd_submit_dualcast(op->chan, op->dst, op->dst2, op->src, op->nbytes,
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op->cb_fn, op->cb_arg);
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break;
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2020-04-29 22:56:11 +00:00
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case IDXD_OPCODE_COMPARE:
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rc = spdk_idxd_submit_compare(op->chan, op->src, op->src2, op->nbytes,
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op->cb_fn, op->cb_arg);
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break;
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2020-04-07 16:38:58 +00:00
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case IDXD_OPCODE_MEMFILL:
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rc = spdk_idxd_submit_fill(op->chan, op->dst, op->fill_pattern, op->nbytes,
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op->cb_fn, op->cb_arg);
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break;
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2020-04-29 17:36:30 +00:00
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case IDXD_OPCODE_CRC32C_GEN:
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rc = spdk_idxd_submit_crc32c(op->chan, op->dst, op->src, op->seed, op->nbytes,
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op->cb_fn, op->cb_arg);
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break;
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2020-05-07 18:45:15 +00:00
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case IDXD_OPCODE_BATCH:
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rc = spdk_idxd_batch_submit(op->chan, op->batch, op->cb_fn, op->cb_arg);
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break;
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2020-04-07 16:38:58 +00:00
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default:
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/* Should never get here */
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assert(false);
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break;
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}
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if (rc == 0) {
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2020-05-07 18:45:15 +00:00
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TAILQ_REMOVE(&chan->queued_ops, op, link);
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2020-04-07 16:38:58 +00:00
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free(op);
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} else {
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/* Busy, resubmit to try again later */
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break;
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}
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}
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return -1;
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}
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static size_t
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accel_engine_idxd_get_ctx_size(void)
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{
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return sizeof(struct idxd_task) + sizeof(struct spdk_accel_task);
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}
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static void
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idxd_done(void *cb_arg, int status)
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{
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struct spdk_accel_task *accel_req;
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struct idxd_task *idxd_task = cb_arg;
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accel_req = SPDK_CONTAINEROF(idxd_task, struct spdk_accel_task,
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offload_ctx);
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idxd_task->cb(accel_req, status);
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}
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2020-04-28 16:12:07 +00:00
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static struct idxd_op *
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_prep_queue_command(struct idxd_io_channel *chan, spdk_accel_completion_cb cb_fn, void *cb_arg)
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{
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struct idxd_op *op_to_queue;
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op_to_queue = calloc(1, sizeof(struct idxd_op));
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if (op_to_queue == NULL) {
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SPDK_ERRLOG("Failed to allocate operation for queueing\n");
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return NULL;
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}
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op_to_queue->chan = chan->chan;
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op_to_queue->cb_fn = cb_fn;
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op_to_queue->cb_arg = cb_arg;
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return op_to_queue;
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}
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2020-04-07 16:38:58 +00:00
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static int
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2020-07-03 14:08:47 +00:00
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idxd_submit_copy(struct spdk_io_channel *ch, void *dst, void *src, uint64_t nbytes,
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spdk_accel_completion_cb cb_fn, void *cb_arg)
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2020-04-07 16:38:58 +00:00
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{
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struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
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struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
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int rc = 0;
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2020-07-03 14:08:47 +00:00
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idxd_task->cb = cb_fn;
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2020-04-07 16:38:58 +00:00
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if (chan->state == IDXD_CHANNEL_ACTIVE) {
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rc = spdk_idxd_submit_copy(chan->chan, dst, src, nbytes, idxd_done, idxd_task);
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}
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if (chan->state == IDXD_CHANNEL_PAUSED || rc == -EBUSY) {
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struct idxd_op *op_to_queue;
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2020-04-28 16:12:07 +00:00
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/* Commpom prep. */
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op_to_queue = _prep_queue_command(chan, idxd_done, idxd_task);
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2020-04-07 16:38:58 +00:00
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if (op_to_queue == NULL) {
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return -ENOMEM;
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}
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2020-04-28 16:12:07 +00:00
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/* Command specific. */
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2020-04-07 16:38:58 +00:00
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op_to_queue->dst = dst;
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op_to_queue->src = src;
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op_to_queue->nbytes = nbytes;
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op_to_queue->op_code = IDXD_OPCODE_MEMMOVE;
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2020-04-28 16:12:07 +00:00
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/* Queue the operation. */
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2020-04-07 16:38:58 +00:00
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TAILQ_INSERT_TAIL(&chan->queued_ops, op_to_queue, link);
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2020-04-29 17:36:30 +00:00
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return 0;
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2020-04-07 16:38:58 +00:00
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} else if (chan->state == IDXD_CHANNEL_ERROR) {
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return -EINVAL;
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}
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return rc;
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}
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2020-04-30 22:07:58 +00:00
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static int
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2020-07-03 14:08:47 +00:00
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idxd_submit_dualcast(struct spdk_io_channel *ch, void *dst1, void *dst2, void *src,
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uint64_t nbytes, spdk_accel_completion_cb cb_fn, void *cb_arg)
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2020-04-30 22:07:58 +00:00
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{
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struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
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struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
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int rc = 0;
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2020-07-03 14:08:47 +00:00
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idxd_task->cb = cb_fn;
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2020-04-30 22:07:58 +00:00
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if (chan->state == IDXD_CHANNEL_ACTIVE) {
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rc = spdk_idxd_submit_dualcast(chan->chan, dst1, dst2, src, nbytes, idxd_done, idxd_task);
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}
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if (chan->state == IDXD_CHANNEL_PAUSED || rc == -EBUSY) {
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struct idxd_op *op_to_queue;
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/* Commpom prep. */
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op_to_queue = _prep_queue_command(chan, idxd_done, idxd_task);
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if (op_to_queue == NULL) {
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return -ENOMEM;
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}
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/* Command specific. */
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op_to_queue->dst = dst1;
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op_to_queue->dst2 = dst2;
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op_to_queue->src = src;
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op_to_queue->nbytes = nbytes;
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op_to_queue->op_code = IDXD_OPCODE_DUALCAST;
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/* Queue the operation. */
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TAILQ_INSERT_TAIL(&chan->queued_ops, op_to_queue, link);
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return 0;
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} else if (chan->state == IDXD_CHANNEL_ERROR) {
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return -EINVAL;
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}
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return rc;
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}
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2020-04-29 22:56:11 +00:00
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static int
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2020-07-03 14:08:47 +00:00
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idxd_submit_compare(struct spdk_io_channel *ch, void *src1, void *src2,
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uint64_t nbytes, spdk_accel_completion_cb cb_fn, void *cb_arg)
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2020-04-29 22:56:11 +00:00
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{
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struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
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struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
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int rc = 0;
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2020-07-03 14:08:47 +00:00
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idxd_task->cb = cb_fn;
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2020-04-29 22:56:11 +00:00
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if (chan->state == IDXD_CHANNEL_ACTIVE) {
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rc = spdk_idxd_submit_compare(chan->chan, src1, src2, nbytes, idxd_done, idxd_task);
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}
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if (chan->state == IDXD_CHANNEL_PAUSED || rc == -EBUSY) {
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struct idxd_op *op_to_queue;
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/* Commpom prep. */
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op_to_queue = _prep_queue_command(chan, idxd_done, idxd_task);
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if (op_to_queue == NULL) {
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return -ENOMEM;
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}
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/* Command specific. */
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op_to_queue->src = src1;
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op_to_queue->src2 = src2;
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|
|
op_to_queue->nbytes = nbytes;
|
|
|
|
op_to_queue->op_code = IDXD_OPCODE_COMPARE;
|
|
|
|
|
|
|
|
/* Queue the operation. */
|
|
|
|
TAILQ_INSERT_TAIL(&chan->queued_ops, op_to_queue, link);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
} else if (chan->state == IDXD_CHANNEL_ERROR) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2020-04-07 16:38:58 +00:00
|
|
|
static int
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_submit_fill(struct spdk_io_channel *ch, void *dst, uint8_t fill,
|
|
|
|
uint64_t nbytes, spdk_accel_completion_cb cb_fn, void *cb_arg)
|
2020-04-07 16:38:58 +00:00
|
|
|
{
|
|
|
|
struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
int rc = 0;
|
|
|
|
uint64_t fill_pattern;
|
|
|
|
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_task->cb = cb_fn;
|
2020-04-07 16:38:58 +00:00
|
|
|
memset(&fill_pattern, fill, sizeof(uint64_t));
|
|
|
|
|
|
|
|
if (chan->state == IDXD_CHANNEL_ACTIVE) {
|
|
|
|
rc = spdk_idxd_submit_fill(chan->chan, dst, fill_pattern, nbytes, idxd_done, idxd_task);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (chan->state == IDXD_CHANNEL_PAUSED || rc == -EBUSY) {
|
|
|
|
struct idxd_op *op_to_queue;
|
|
|
|
|
2020-04-28 16:12:07 +00:00
|
|
|
/* Commpom prep. */
|
|
|
|
op_to_queue = _prep_queue_command(chan, idxd_done, idxd_task);
|
2020-04-07 16:38:58 +00:00
|
|
|
if (op_to_queue == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
2020-04-28 16:12:07 +00:00
|
|
|
|
|
|
|
/* Command specific. */
|
2020-04-07 16:38:58 +00:00
|
|
|
op_to_queue->dst = dst;
|
|
|
|
op_to_queue->fill_pattern = fill_pattern;
|
|
|
|
op_to_queue->nbytes = nbytes;
|
|
|
|
op_to_queue->op_code = IDXD_OPCODE_MEMFILL;
|
|
|
|
|
2020-04-28 16:12:07 +00:00
|
|
|
/* Queue the operation. */
|
2020-04-07 16:38:58 +00:00
|
|
|
TAILQ_INSERT_TAIL(&chan->queued_ops, op_to_queue, link);
|
2020-04-29 17:36:30 +00:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
} else if (chan->state == IDXD_CHANNEL_ERROR) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_submit_crc32c(struct spdk_io_channel *ch, uint32_t *dst, void *src,
|
|
|
|
uint32_t seed, uint64_t nbytes, spdk_accel_completion_cb cb_fn, void *cb_arg)
|
2020-04-29 17:36:30 +00:00
|
|
|
{
|
|
|
|
struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
int rc = 0;
|
|
|
|
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_task->cb = cb_fn;
|
2020-04-29 17:36:30 +00:00
|
|
|
|
|
|
|
if (chan->state == IDXD_CHANNEL_ACTIVE) {
|
|
|
|
rc = spdk_idxd_submit_crc32c(chan->chan, dst, src, seed, nbytes, idxd_done, idxd_task);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (chan->state == IDXD_CHANNEL_PAUSED || rc == -EBUSY) {
|
|
|
|
struct idxd_op *op_to_queue;
|
|
|
|
|
|
|
|
/* Commpom prep. */
|
|
|
|
op_to_queue = _prep_queue_command(chan, idxd_done, idxd_task);
|
|
|
|
if (op_to_queue == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Command specific. */
|
|
|
|
op_to_queue->dst = dst;
|
|
|
|
op_to_queue->src = src;
|
|
|
|
op_to_queue->seed = seed;
|
|
|
|
op_to_queue->nbytes = nbytes;
|
|
|
|
op_to_queue->op_code = IDXD_OPCODE_CRC32C_GEN;
|
|
|
|
|
|
|
|
/* Queue the operation. */
|
|
|
|
TAILQ_INSERT_TAIL(&chan->queued_ops, op_to_queue, link);
|
|
|
|
return 0;
|
|
|
|
|
2020-04-07 16:38:58 +00:00
|
|
|
} else if (chan->state == IDXD_CHANNEL_ERROR) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2020-04-24 16:47:55 +00:00
|
|
|
static uint64_t
|
|
|
|
idxd_get_capabilities(void)
|
|
|
|
{
|
2020-04-30 22:07:58 +00:00
|
|
|
return ACCEL_COPY | ACCEL_FILL | ACCEL_CRC32C | ACCEL_COMPARE |
|
2020-05-07 18:45:15 +00:00
|
|
|
ACCEL_DUALCAST | ACCEL_BATCH;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint32_t
|
|
|
|
idxd_batch_get_max(void)
|
|
|
|
{
|
|
|
|
return spdk_idxd_batch_get_max();
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct spdk_accel_batch *
|
|
|
|
idxd_batch_start(struct spdk_io_channel *ch)
|
|
|
|
{
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
|
|
|
|
return (struct spdk_accel_batch *)spdk_idxd_batch_create(chan->chan);
|
|
|
|
}
|
|
|
|
|
2020-07-16 22:47:59 +00:00
|
|
|
static int
|
|
|
|
idxd_batch_cancel(struct spdk_io_channel *ch, struct spdk_accel_batch *_batch)
|
|
|
|
{
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
struct idxd_batch *batch = (struct idxd_batch *)_batch;
|
|
|
|
|
|
|
|
return spdk_idxd_batch_cancel(chan->chan, batch);
|
|
|
|
}
|
|
|
|
|
2020-05-07 18:45:15 +00:00
|
|
|
static int
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_batch_submit(struct spdk_io_channel *ch, struct spdk_accel_batch *_batch,
|
|
|
|
spdk_accel_completion_cb cb_fn, void *cb_arg)
|
2020-05-07 18:45:15 +00:00
|
|
|
{
|
|
|
|
struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
struct idxd_batch *batch = (struct idxd_batch *)_batch;
|
|
|
|
int rc = 0;
|
|
|
|
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_task->cb = cb_fn;
|
2020-05-07 18:45:15 +00:00
|
|
|
|
|
|
|
if (chan->state == IDXD_CHANNEL_ACTIVE) {
|
|
|
|
rc = spdk_idxd_batch_submit(chan->chan, batch, idxd_done, idxd_task);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (chan->state == IDXD_CHANNEL_PAUSED || rc == -EBUSY) {
|
|
|
|
struct idxd_op *op_to_queue;
|
|
|
|
|
|
|
|
/* Commpom prep. */
|
|
|
|
op_to_queue = _prep_queue_command(chan, idxd_done, idxd_task);
|
|
|
|
if (op_to_queue == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Command specific. */
|
|
|
|
op_to_queue->batch = batch;
|
|
|
|
op_to_queue->op_code = IDXD_OPCODE_BATCH;
|
|
|
|
|
|
|
|
/* Queue the operation. */
|
|
|
|
TAILQ_INSERT_TAIL(&chan->queued_ops, op_to_queue, link);
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
} else if (chan->state == IDXD_CHANNEL_ERROR) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_batch_prep_copy(struct spdk_io_channel *ch, struct spdk_accel_batch *_batch,
|
|
|
|
void *dst, void *src, uint64_t nbytes, spdk_accel_completion_cb cb_fn, void *cb_arg)
|
2020-05-07 18:45:15 +00:00
|
|
|
{
|
|
|
|
struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
struct idxd_batch *batch = (struct idxd_batch *)_batch;
|
|
|
|
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_task->cb = cb_fn;
|
2020-05-07 18:45:15 +00:00
|
|
|
|
|
|
|
return spdk_idxd_batch_prep_copy(chan->chan, batch, dst, src, nbytes,
|
|
|
|
idxd_done, idxd_task);
|
2020-04-24 16:47:55 +00:00
|
|
|
}
|
|
|
|
|
2020-06-18 20:39:28 +00:00
|
|
|
static int
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_batch_prep_fill(struct spdk_io_channel *ch, struct spdk_accel_batch *_batch,
|
|
|
|
void *dst, uint8_t fill, uint64_t nbytes, spdk_accel_completion_cb cb_fn, void *cb_arg)
|
2020-06-18 20:39:28 +00:00
|
|
|
{
|
|
|
|
struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
uint64_t fill_pattern;
|
|
|
|
struct idxd_batch *batch = (struct idxd_batch *)_batch;
|
|
|
|
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_task->cb = cb_fn;
|
2020-06-18 20:39:28 +00:00
|
|
|
memset(&fill_pattern, fill, sizeof(uint64_t));
|
|
|
|
|
|
|
|
return spdk_idxd_batch_prep_fill(chan->chan, batch, dst, fill_pattern, nbytes, idxd_done,
|
|
|
|
idxd_task);
|
|
|
|
}
|
|
|
|
|
2020-06-16 17:24:35 +00:00
|
|
|
static int
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_batch_prep_dualcast(struct spdk_io_channel *ch, struct spdk_accel_batch *_batch,
|
|
|
|
void *dst1, void *dst2, void *src, uint64_t nbytes,
|
|
|
|
spdk_accel_completion_cb cb_fn, void *cb_arg)
|
2020-06-16 17:24:35 +00:00
|
|
|
{
|
|
|
|
struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
struct idxd_batch *batch = (struct idxd_batch *)_batch;
|
|
|
|
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_task->cb = cb_fn;
|
2020-06-16 17:24:35 +00:00
|
|
|
|
|
|
|
return spdk_idxd_batch_prep_dualcast(chan->chan, batch, dst1, dst2, src, nbytes, idxd_done,
|
|
|
|
idxd_task);
|
|
|
|
}
|
|
|
|
|
2020-06-18 22:17:37 +00:00
|
|
|
static int
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_batch_prep_crc32c(struct spdk_io_channel *ch, struct spdk_accel_batch *_batch,
|
2020-06-18 22:17:37 +00:00
|
|
|
uint32_t *dst, void *src, uint32_t seed, uint64_t nbytes,
|
2020-07-03 14:08:47 +00:00
|
|
|
spdk_accel_completion_cb cb_fn, void *cb_arg)
|
2020-06-18 22:17:37 +00:00
|
|
|
{
|
|
|
|
struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
struct idxd_batch *batch = (struct idxd_batch *)_batch;
|
|
|
|
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_task->cb = cb_fn;
|
2020-06-18 22:17:37 +00:00
|
|
|
|
|
|
|
return spdk_idxd_batch_prep_crc32c(chan->chan, batch, dst, src, seed, nbytes, idxd_done,
|
|
|
|
idxd_task);
|
|
|
|
}
|
|
|
|
|
2020-06-18 22:46:27 +00:00
|
|
|
static int
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_batch_prep_compare(struct spdk_io_channel *ch, struct spdk_accel_batch *_batch,
|
|
|
|
void *src1, void *src2, uint64_t nbytes, spdk_accel_completion_cb cb_fn, void *cb_arg)
|
2020-06-18 22:46:27 +00:00
|
|
|
{
|
|
|
|
struct idxd_task *idxd_task = (struct idxd_task *)cb_arg;
|
|
|
|
struct idxd_io_channel *chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
struct idxd_batch *batch = (struct idxd_batch *)_batch;
|
|
|
|
|
2020-07-03 14:08:47 +00:00
|
|
|
idxd_task->cb = cb_fn;
|
2020-06-18 22:46:27 +00:00
|
|
|
|
|
|
|
return spdk_idxd_batch_prep_compare(chan->chan, batch, src1, src2, nbytes, idxd_done,
|
|
|
|
idxd_task);
|
|
|
|
}
|
|
|
|
|
2020-04-24 16:47:55 +00:00
|
|
|
static struct spdk_accel_engine idxd_accel_engine = {
|
|
|
|
.get_capabilities = idxd_get_capabilities,
|
|
|
|
.copy = idxd_submit_copy,
|
2020-05-07 18:45:15 +00:00
|
|
|
.batch_get_max = idxd_batch_get_max,
|
|
|
|
.batch_create = idxd_batch_start,
|
2020-07-16 22:47:59 +00:00
|
|
|
.batch_cancel = idxd_batch_cancel,
|
2020-05-07 18:45:15 +00:00
|
|
|
.batch_prep_copy = idxd_batch_prep_copy,
|
2020-06-18 20:39:28 +00:00
|
|
|
.batch_prep_fill = idxd_batch_prep_fill,
|
2020-06-16 17:24:35 +00:00
|
|
|
.batch_prep_dualcast = idxd_batch_prep_dualcast,
|
2020-06-18 22:17:37 +00:00
|
|
|
.batch_prep_crc32c = idxd_batch_prep_crc32c,
|
2020-06-18 22:46:27 +00:00
|
|
|
.batch_prep_compare = idxd_batch_prep_compare,
|
2020-05-07 18:45:15 +00:00
|
|
|
.batch_submit = idxd_batch_submit,
|
2020-04-30 22:07:58 +00:00
|
|
|
.dualcast = idxd_submit_dualcast,
|
2020-04-29 22:56:11 +00:00
|
|
|
.compare = idxd_submit_compare,
|
2020-04-24 16:47:55 +00:00
|
|
|
.fill = idxd_submit_fill,
|
2020-04-29 17:36:30 +00:00
|
|
|
.crc32c = idxd_submit_crc32c,
|
2020-04-24 16:47:55 +00:00
|
|
|
.get_io_channel = idxd_get_io_channel,
|
|
|
|
};
|
2020-04-07 16:38:58 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure the max number of descriptors that a channel is
|
|
|
|
* allowed to use based on the total number of current channels.
|
|
|
|
* This is to allow for dynamic load balancing for hw flow control.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
_config_max_desc(struct spdk_io_channel_iter *i)
|
|
|
|
{
|
|
|
|
struct idxd_io_channel *chan;
|
|
|
|
struct spdk_io_channel *ch;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
ch = spdk_io_channel_iter_get_channel(i);
|
|
|
|
chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
|
2020-07-02 14:45:28 +00:00
|
|
|
pthread_mutex_lock(&g_configuration_lock);
|
2020-04-07 16:38:58 +00:00
|
|
|
rc = spdk_idxd_reconfigure_chan(chan->chan, chan->dev->num_channels);
|
2020-07-02 14:45:28 +00:00
|
|
|
pthread_mutex_unlock(&g_configuration_lock);
|
2020-04-07 16:38:58 +00:00
|
|
|
if (rc == 0) {
|
|
|
|
chan->state = IDXD_CHANNEL_ACTIVE;
|
|
|
|
} else {
|
|
|
|
chan->state = IDXD_CHANNEL_ERROR;
|
|
|
|
}
|
|
|
|
|
|
|
|
spdk_for_each_channel_continue(i, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Pauses a channel so that it can be re-configured. */
|
|
|
|
static void
|
|
|
|
_pause_chan(struct spdk_io_channel_iter *i)
|
|
|
|
{
|
|
|
|
struct idxd_io_channel *chan;
|
|
|
|
struct spdk_io_channel *ch;
|
|
|
|
|
|
|
|
ch = spdk_io_channel_iter_get_channel(i);
|
|
|
|
chan = spdk_io_channel_get_ctx(ch);
|
|
|
|
|
|
|
|
/* start queueing up new requests. */
|
|
|
|
chan->state = IDXD_CHANNEL_PAUSED;
|
|
|
|
|
|
|
|
spdk_for_each_channel_continue(i, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
_pause_chan_done(struct spdk_io_channel_iter *i, int status)
|
|
|
|
{
|
2020-05-07 18:45:15 +00:00
|
|
|
spdk_for_each_channel(&idxd_accel_engine, _config_max_desc, NULL, NULL);
|
2020-04-07 16:38:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
idxd_create_cb(void *io_device, void *ctx_buf)
|
|
|
|
{
|
|
|
|
struct idxd_io_channel *chan = ctx_buf;
|
|
|
|
struct idxd_device *dev;
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
dev = idxd_select_device();
|
|
|
|
if (dev == NULL) {
|
|
|
|
SPDK_ERRLOG("Failed to allocate idxd_device\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
chan->chan = spdk_idxd_get_channel(dev->idxd);
|
|
|
|
if (chan->chan == NULL) {
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
chan->dev = dev;
|
|
|
|
chan->poller = spdk_poller_register(idxd_poll, chan, 0);
|
|
|
|
TAILQ_INIT(&chan->queued_ops);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure the channel but leave paused until all others
|
|
|
|
* are paused and re-configured based on the new number of
|
|
|
|
* channels. This enables dynamic load balancing for HW
|
|
|
|
* flow control.
|
|
|
|
*/
|
2020-07-02 14:45:28 +00:00
|
|
|
pthread_mutex_lock(&g_configuration_lock);
|
2020-04-07 16:38:58 +00:00
|
|
|
rc = spdk_idxd_configure_chan(chan->chan);
|
|
|
|
if (rc) {
|
|
|
|
SPDK_ERRLOG("Failed to configure new channel rc = %d\n", rc);
|
|
|
|
chan->state = IDXD_CHANNEL_ERROR;
|
|
|
|
spdk_poller_unregister(&chan->poller);
|
2020-07-02 14:45:28 +00:00
|
|
|
pthread_mutex_unlock(&g_configuration_lock);
|
2020-04-07 16:38:58 +00:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
|
|
|
chan->state = IDXD_CHANNEL_PAUSED;
|
|
|
|
chan->dev->num_channels++;
|
2020-07-02 14:45:28 +00:00
|
|
|
pthread_mutex_unlock(&g_configuration_lock);
|
2020-04-07 16:38:58 +00:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Pause all channels so that we can set proper flow control
|
|
|
|
* per channel. When all are paused, we'll update the max
|
|
|
|
* number of descriptors allowed per channel.
|
|
|
|
*/
|
|
|
|
spdk_for_each_channel(&idxd_accel_engine, _pause_chan, NULL,
|
|
|
|
_pause_chan_done);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
_pause_chan_destroy_done(struct spdk_io_channel_iter *i, int status)
|
|
|
|
{
|
|
|
|
/* Rebalance the rings with the smaller number of remaining channels. */
|
2020-05-07 18:45:15 +00:00
|
|
|
spdk_for_each_channel(&idxd_accel_engine, _config_max_desc, NULL, NULL);
|
2020-04-07 16:38:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
idxd_destroy_cb(void *io_device, void *ctx_buf)
|
|
|
|
{
|
|
|
|
struct idxd_io_channel *chan = ctx_buf;
|
|
|
|
|
2020-07-02 14:45:28 +00:00
|
|
|
pthread_mutex_lock(&g_configuration_lock);
|
2020-04-07 16:38:58 +00:00
|
|
|
assert(chan->dev->num_channels > 0);
|
|
|
|
chan->dev->num_channels--;
|
|
|
|
spdk_idxd_reconfigure_chan(chan->chan, 0);
|
2020-07-02 14:45:28 +00:00
|
|
|
pthread_mutex_unlock(&g_configuration_lock);
|
|
|
|
|
2020-04-07 16:38:58 +00:00
|
|
|
spdk_poller_unregister(&chan->poller);
|
|
|
|
spdk_idxd_put_channel(chan->chan);
|
|
|
|
|
|
|
|
/* Pause each channel then rebalance the max number of ring slots. */
|
|
|
|
spdk_for_each_channel(&idxd_accel_engine, _pause_chan, NULL,
|
|
|
|
_pause_chan_destroy_done);
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct spdk_io_channel *
|
|
|
|
idxd_get_io_channel(void)
|
|
|
|
{
|
|
|
|
return spdk_get_io_channel(&idxd_accel_engine);
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
probe_cb(void *cb_ctx, struct spdk_pci_device *pci_dev)
|
|
|
|
{
|
|
|
|
struct spdk_pci_addr pci_addr = spdk_pci_device_get_addr(pci_dev);
|
|
|
|
struct pci_device *pdev;
|
|
|
|
|
|
|
|
SPDK_NOTICELOG(
|
|
|
|
" Found matching device at %04x:%02x:%02x.%x vendor:0x%04x device:0x%04x\n",
|
|
|
|
pci_addr.domain,
|
|
|
|
pci_addr.bus,
|
|
|
|
pci_addr.dev,
|
|
|
|
pci_addr.func,
|
|
|
|
spdk_pci_device_get_vendor_id(pci_dev),
|
|
|
|
spdk_pci_device_get_device_id(pci_dev));
|
|
|
|
|
|
|
|
pdev = calloc(1, sizeof(*pdev));
|
|
|
|
if (pdev == NULL) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
pdev->pci_dev = pci_dev;
|
|
|
|
TAILQ_INSERT_TAIL(&g_pci_devices, pdev, tailq);
|
|
|
|
|
|
|
|
/* Claim the device in case conflict with other process */
|
|
|
|
if (spdk_pci_device_claim(pci_dev) < 0) {
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
attach_cb(void *cb_ctx, struct spdk_pci_device *pci_dev, struct spdk_idxd_device *idxd)
|
|
|
|
{
|
|
|
|
struct idxd_device *dev;
|
|
|
|
|
|
|
|
dev = calloc(1, sizeof(*dev));
|
|
|
|
if (dev == NULL) {
|
|
|
|
SPDK_ERRLOG("Failed to allocate device struct\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev->idxd = idxd;
|
|
|
|
if (g_next_dev == NULL) {
|
|
|
|
g_next_dev = dev;
|
|
|
|
}
|
|
|
|
|
|
|
|
TAILQ_INSERT_TAIL(&g_idxd_devices, dev, tailq);
|
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
accel_engine_idxd_enable_probe(uint32_t config_number)
|
|
|
|
{
|
|
|
|
if (config_number > IDXD_MAX_CONFIG_NUM) {
|
|
|
|
SPDK_ERRLOG("Invalid config number, using default of 0\n");
|
|
|
|
config_number = 0;
|
|
|
|
}
|
|
|
|
|
2020-04-27 15:45:46 +00:00
|
|
|
g_config_number = config_number;
|
2020-04-07 16:38:58 +00:00
|
|
|
g_idxd_enable = true;
|
2020-04-27 15:45:46 +00:00
|
|
|
spdk_idxd_set_config(g_config_number);
|
2020-04-07 16:38:58 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
accel_engine_idxd_init(void)
|
|
|
|
{
|
|
|
|
if (!g_idxd_enable) {
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (spdk_idxd_probe(NULL, probe_cb, attach_cb) != 0) {
|
|
|
|
SPDK_ERRLOG("spdk_idxd_probe() failed\n");
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
|
|
|
|
g_idxd_initialized = true;
|
2020-04-24 18:33:12 +00:00
|
|
|
SPDK_NOTICELOG("Accel engine updated to use IDXD DSA engine.\n");
|
2020-04-07 16:38:58 +00:00
|
|
|
spdk_accel_hw_engine_register(&idxd_accel_engine);
|
|
|
|
spdk_io_device_register(&idxd_accel_engine, idxd_create_cb, idxd_destroy_cb,
|
|
|
|
sizeof(struct idxd_io_channel), "idxd_accel_engine");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
accel_engine_idxd_exit(void *ctx)
|
|
|
|
{
|
|
|
|
struct idxd_device *dev;
|
|
|
|
struct pci_device *pci_dev;
|
|
|
|
|
|
|
|
if (g_idxd_initialized) {
|
|
|
|
spdk_io_device_unregister(&idxd_accel_engine, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
while (!TAILQ_EMPTY(&g_idxd_devices)) {
|
|
|
|
dev = TAILQ_FIRST(&g_idxd_devices);
|
|
|
|
TAILQ_REMOVE(&g_idxd_devices, dev, tailq);
|
|
|
|
spdk_idxd_detach(dev->idxd);
|
|
|
|
free(dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
while (!TAILQ_EMPTY(&g_pci_devices)) {
|
|
|
|
pci_dev = TAILQ_FIRST(&g_pci_devices);
|
|
|
|
TAILQ_REMOVE(&g_pci_devices, pci_dev, tailq);
|
|
|
|
spdk_pci_device_detach(pci_dev->pci_dev);
|
|
|
|
free(pci_dev);
|
|
|
|
}
|
|
|
|
|
|
|
|
spdk_accel_engine_module_finish();
|
|
|
|
}
|
|
|
|
|
2020-04-27 15:45:46 +00:00
|
|
|
static void
|
|
|
|
accel_engine_idxd_write_config_json(struct spdk_json_write_ctx *w)
|
|
|
|
{
|
|
|
|
if (g_idxd_enable) {
|
|
|
|
spdk_json_write_object_begin(w);
|
|
|
|
spdk_json_write_named_string(w, "method", "idxd_scan_accel_engine");
|
|
|
|
spdk_json_write_named_object_begin(w, "params");
|
|
|
|
spdk_json_write_named_uint32(w, "config_number", g_config_number);
|
|
|
|
spdk_json_write_object_end(w);
|
|
|
|
spdk_json_write_object_end(w);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2020-04-07 16:38:58 +00:00
|
|
|
SPDK_ACCEL_MODULE_REGISTER(accel_engine_idxd_init, accel_engine_idxd_exit,
|
2020-04-27 15:45:46 +00:00
|
|
|
NULL, accel_engine_idxd_write_config_json,
|
2020-04-07 16:38:58 +00:00
|
|
|
accel_engine_idxd_get_ctx_size)
|
|
|
|
|
|
|
|
SPDK_LOG_REGISTER_COMPONENT("accel_idxd", SPDK_LOG_ACCEL_IDXD)
|