2017-01-05 23:12:54 +00:00
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/*-
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* BSD LICENSE
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*
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* Copyright (c) Intel Corporation.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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2017-05-02 18:18:25 +00:00
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#include "spdk/stdinc.h"
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2017-01-05 23:12:54 +00:00
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#include "spdk_cunit.h"
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2019-11-22 22:14:25 +00:00
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#define UNIT_TEST_NO_VTOPHYS
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2017-01-05 23:12:54 +00:00
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#include "nvme/nvme_pcie.c"
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2020-01-07 21:18:38 +00:00
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#include "common/lib/nvme/common_stubs.h"
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2019-12-23 19:58:27 +00:00
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2019-12-26 17:10:02 +00:00
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pid_t g_spdk_nvme_pid;
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DEFINE_STUB(spdk_mem_register, int, (void *vaddr, size_t len), 0);
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DEFINE_STUB(spdk_mem_unregister, int, (void *vaddr, size_t len), 0);
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DEFINE_STUB(nvme_get_quirks, uint64_t, (const struct spdk_pci_id *id), 0);
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2020-05-15 03:50:18 +00:00
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DEFINE_STUB(nvme_wait_for_completion, int,
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2019-12-26 17:10:02 +00:00
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(struct spdk_nvme_qpair *qpair,
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struct nvme_completion_poll_status *status), 0);
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DEFINE_STUB_V(nvme_completion_poll_cb, (void *arg, const struct spdk_nvme_cpl *cpl));
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DEFINE_STUB(nvme_ctrlr_submit_admin_request, int, (struct spdk_nvme_ctrlr *ctrlr,
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struct nvme_request *req), 0);
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DEFINE_STUB_V(nvme_ctrlr_free_processes, (struct spdk_nvme_ctrlr *ctrlr));
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DEFINE_STUB(nvme_ctrlr_proc_get_devhandle, struct spdk_pci_device *,
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(struct spdk_nvme_ctrlr *ctrlr), NULL);
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DEFINE_STUB(spdk_pci_device_map_bar, int, (struct spdk_pci_device *dev, uint32_t bar,
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void **mapped_addr, uint64_t *phys_addr, uint64_t *size), 0);
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DEFINE_STUB(spdk_pci_device_unmap_bar, int, (struct spdk_pci_device *dev, uint32_t bar, void *addr),
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0);
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DEFINE_STUB(spdk_pci_device_attach, int, (struct spdk_pci_driver *driver, spdk_pci_enum_cb enum_cb,
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void *enum_ctx, struct spdk_pci_addr *pci_address), 0);
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DEFINE_STUB(spdk_pci_device_claim, int, (struct spdk_pci_device *dev), 0);
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DEFINE_STUB_V(spdk_pci_device_unclaim, (struct spdk_pci_device *dev));
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DEFINE_STUB_V(spdk_pci_device_detach, (struct spdk_pci_device *device));
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2020-05-25 06:47:21 +00:00
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DEFINE_STUB(spdk_pci_device_cfg_write16, int, (struct spdk_pci_device *dev, uint16_t value,
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2019-12-26 17:10:02 +00:00
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uint32_t offset), 0);
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2020-05-25 06:47:21 +00:00
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DEFINE_STUB(spdk_pci_device_cfg_read16, int, (struct spdk_pci_device *dev, uint16_t *value,
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2019-12-26 17:10:02 +00:00
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uint32_t offset), 0);
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DEFINE_STUB(spdk_pci_device_get_id, struct spdk_pci_id, (struct spdk_pci_device *dev), {0})
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2020-05-15 03:50:18 +00:00
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DEFINE_STUB(nvme_uevent_connect, int, (void), 0);
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2019-12-26 17:10:02 +00:00
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2018-11-17 13:31:45 +00:00
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struct spdk_log_flag SPDK_LOG_NVME = {
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2017-01-05 23:12:54 +00:00
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.name = "nvme",
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.enabled = false,
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};
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2019-11-25 18:21:39 +00:00
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struct nvme_driver *g_spdk_nvme_driver = NULL;
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2019-10-31 14:42:48 +00:00
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bool g_device_is_enumerated = false;
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2017-01-05 23:12:54 +00:00
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void
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nvme_ctrlr_fail(struct spdk_nvme_ctrlr *ctrlr, bool hot_remove)
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{
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2019-10-31 14:42:48 +00:00
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CU_ASSERT(ctrlr != NULL);
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if (hot_remove) {
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ctrlr->is_removed = true;
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}
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ctrlr->is_failed = true;
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2017-01-05 23:12:54 +00:00
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}
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2019-11-25 18:21:39 +00:00
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struct spdk_uevent_entry {
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struct spdk_uevent uevent;
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STAILQ_ENTRY(spdk_uevent_entry) link;
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};
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static STAILQ_HEAD(, spdk_uevent_entry) g_uevents = STAILQ_HEAD_INITIALIZER(g_uevents);
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2017-01-05 23:12:54 +00:00
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int
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2020-05-15 03:50:18 +00:00
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nvme_get_uevent(int fd, struct spdk_uevent *uevent)
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2017-01-05 23:12:54 +00:00
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{
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2019-11-25 18:21:39 +00:00
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struct spdk_uevent_entry *entry;
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2019-10-31 14:42:48 +00:00
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2019-11-25 18:21:39 +00:00
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if (STAILQ_EMPTY(&g_uevents)) {
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return 0;
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2019-10-31 14:42:48 +00:00
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}
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2019-11-25 18:21:39 +00:00
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entry = STAILQ_FIRST(&g_uevents);
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STAILQ_REMOVE_HEAD(&g_uevents, link);
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2019-10-31 14:42:48 +00:00
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2019-11-25 18:21:39 +00:00
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*uevent = entry->uevent;
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2019-10-31 14:42:48 +00:00
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2019-11-25 18:21:39 +00:00
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return 1;
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2017-01-05 23:12:54 +00:00
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}
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int
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2018-12-07 10:28:47 +00:00
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spdk_pci_enumerate(struct spdk_pci_driver *driver, spdk_pci_enum_cb enum_cb, void *enum_ctx)
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2017-01-05 23:12:54 +00:00
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{
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2019-10-31 14:42:48 +00:00
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g_device_is_enumerated = true;
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return 0;
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2017-01-05 23:12:54 +00:00
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}
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2019-11-22 22:14:25 +00:00
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static uint64_t g_vtophys_size = 0;
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DEFINE_RETURN_MOCK(spdk_vtophys, uint64_t);
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uint64_t
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spdk_vtophys(void *buf, uint64_t *size)
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{
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if (size) {
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*size = g_vtophys_size;
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}
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HANDLE_RETURN_MOCK(spdk_vtophys);
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return (uintptr_t)buf;
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}
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2019-11-25 18:31:05 +00:00
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DEFINE_STUB(spdk_pci_device_get_addr, struct spdk_pci_addr, (struct spdk_pci_device *dev), {});
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DEFINE_STUB(nvme_ctrlr_probe, int, (const struct spdk_nvme_transport_id *trid,
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struct spdk_nvme_probe_ctx *probe_ctx, void *devhandle), 0);
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2019-11-25 18:21:39 +00:00
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DEFINE_STUB(spdk_pci_device_is_removed, bool, (struct spdk_pci_device *dev), false);
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2020-05-10 23:32:35 +00:00
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DEFINE_STUB(nvme_get_ctrlr_by_trid_unsafe, struct spdk_nvme_ctrlr *,
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2019-11-25 18:21:39 +00:00
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(const struct spdk_nvme_transport_id *trid), NULL);
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2019-11-25 18:31:05 +00:00
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DEFINE_STUB(spdk_nvme_ctrlr_get_regs_csts, union spdk_nvme_csts_register,
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(struct spdk_nvme_ctrlr *ctrlr), {});
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2020-05-15 03:50:18 +00:00
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DEFINE_STUB(nvme_ctrlr_get_process, struct spdk_nvme_ctrlr_process *,
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2019-11-22 22:14:25 +00:00
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(struct spdk_nvme_ctrlr *ctrlr, pid_t pid), NULL);
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DEFINE_STUB(nvme_completion_is_retry, bool, (const struct spdk_nvme_cpl *cpl), false);
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DEFINE_STUB_V(spdk_nvme_qpair_print_command, (struct spdk_nvme_qpair *qpair,
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struct spdk_nvme_cmd *cmd));
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DEFINE_STUB_V(spdk_nvme_qpair_print_completion, (struct spdk_nvme_qpair *qpair,
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struct spdk_nvme_cpl *cpl));
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2017-01-05 23:12:54 +00:00
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2017-07-28 01:32:55 +00:00
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static void
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prp_list_prep(struct nvme_tracker *tr, struct nvme_request *req, uint32_t *prp_index)
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{
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memset(req, 0, sizeof(*req));
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memset(tr, 0, sizeof(*tr));
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tr->req = req;
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tr->prp_sgl_bus_addr = 0xDEADBEEF;
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*prp_index = 0;
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}
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static void
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test_prp_list_append(void)
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{
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struct nvme_request req;
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struct nvme_tracker tr;
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uint32_t prp_index;
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/* Non-DWORD-aligned buffer (invalid) */
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prp_list_prep(&tr, &req, &prp_index);
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2019-11-01 18:16:43 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100001, 0x1000, 0x1000) == -EFAULT);
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2017-07-28 01:32:55 +00:00
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/* 512-byte buffer, 4K aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100000, 0x200, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 1);
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CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x100000);
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/* 512-byte buffer, non-4K-aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x108000, 0x200, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 1);
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CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x108000);
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/* 4K buffer, 4K aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100000, 0x1000, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 1);
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CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x100000);
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/* 4K buffer, non-4K aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100800, 0x1000, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 2);
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CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x100800);
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CU_ASSERT(req.cmd.dptr.prp.prp2 == 0x101000);
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/* 8K buffer, 4K aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100000, 0x2000, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 2);
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CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x100000);
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CU_ASSERT(req.cmd.dptr.prp.prp2 == 0x101000);
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/* 8K buffer, non-4K aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100800, 0x2000, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 3);
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CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x100800);
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CU_ASSERT(req.cmd.dptr.prp.prp2 == tr.prp_sgl_bus_addr);
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CU_ASSERT(tr.u.prp[0] == 0x101000);
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CU_ASSERT(tr.u.prp[1] == 0x102000);
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/* 12K buffer, 4K aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100000, 0x3000, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 3);
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CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x100000);
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CU_ASSERT(req.cmd.dptr.prp.prp2 == tr.prp_sgl_bus_addr);
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CU_ASSERT(tr.u.prp[0] == 0x101000);
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CU_ASSERT(tr.u.prp[1] == 0x102000);
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/* 12K buffer, non-4K aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100800, 0x3000, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 4);
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CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x100800);
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CU_ASSERT(req.cmd.dptr.prp.prp2 == tr.prp_sgl_bus_addr);
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CU_ASSERT(tr.u.prp[0] == 0x101000);
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CU_ASSERT(tr.u.prp[1] == 0x102000);
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CU_ASSERT(tr.u.prp[2] == 0x103000);
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/* Two 4K buffers, both 4K aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100000, 0x1000, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 1);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x900000, 0x1000, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 2);
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CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x100000);
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CU_ASSERT(req.cmd.dptr.prp.prp2 == 0x900000);
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/* Two 4K buffers, first non-4K aligned, second 4K aligned */
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prp_list_prep(&tr, &req, &prp_index);
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2017-08-15 23:22:11 +00:00
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CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100800, 0x1000, 0x1000) == 0);
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2017-07-28 01:32:55 +00:00
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CU_ASSERT(prp_index == 2);
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2017-08-15 23:22:11 +00:00
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|
|
CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x900000, 0x1000, 0x1000) == 0);
|
2017-07-28 01:32:55 +00:00
|
|
|
CU_ASSERT(prp_index == 3);
|
|
|
|
CU_ASSERT(req.cmd.dptr.prp.prp1 == 0x100800);
|
|
|
|
CU_ASSERT(req.cmd.dptr.prp.prp2 == tr.prp_sgl_bus_addr);
|
|
|
|
CU_ASSERT(tr.u.prp[0] == 0x101000);
|
|
|
|
CU_ASSERT(tr.u.prp[1] == 0x900000);
|
|
|
|
|
|
|
|
/* Two 4K buffers, both non-4K aligned (invalid) */
|
|
|
|
prp_list_prep(&tr, &req, &prp_index);
|
2017-08-15 23:22:11 +00:00
|
|
|
CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100800, 0x1000, 0x1000) == 0);
|
2017-07-28 01:32:55 +00:00
|
|
|
CU_ASSERT(prp_index == 2);
|
2019-11-01 18:16:43 +00:00
|
|
|
CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x900800, 0x1000, 0x1000) == -EFAULT);
|
2017-07-28 01:32:55 +00:00
|
|
|
CU_ASSERT(prp_index == 2);
|
|
|
|
|
|
|
|
/* 4K buffer, 4K aligned, but vtophys fails */
|
2018-07-10 17:47:14 +00:00
|
|
|
MOCK_SET(spdk_vtophys, SPDK_VTOPHYS_ERROR);
|
2017-07-28 01:32:55 +00:00
|
|
|
prp_list_prep(&tr, &req, &prp_index);
|
2019-11-01 18:16:43 +00:00
|
|
|
CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100000, 0x1000, 0x1000) == -EFAULT);
|
2018-07-10 17:47:14 +00:00
|
|
|
MOCK_CLEAR(spdk_vtophys);
|
2017-07-28 01:32:55 +00:00
|
|
|
|
|
|
|
/* Largest aligned buffer that can be described in NVME_MAX_PRP_LIST_ENTRIES (plus PRP1) */
|
|
|
|
prp_list_prep(&tr, &req, &prp_index);
|
|
|
|
CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100000,
|
2017-08-15 23:22:11 +00:00
|
|
|
(NVME_MAX_PRP_LIST_ENTRIES + 1) * 0x1000, 0x1000) == 0);
|
2017-07-28 01:32:55 +00:00
|
|
|
CU_ASSERT(prp_index == NVME_MAX_PRP_LIST_ENTRIES + 1);
|
|
|
|
|
|
|
|
/* Largest non-4K-aligned buffer that can be described in NVME_MAX_PRP_LIST_ENTRIES (plus PRP1) */
|
|
|
|
prp_list_prep(&tr, &req, &prp_index);
|
|
|
|
CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100800,
|
2017-08-15 23:22:11 +00:00
|
|
|
NVME_MAX_PRP_LIST_ENTRIES * 0x1000, 0x1000) == 0);
|
2017-07-28 01:32:55 +00:00
|
|
|
CU_ASSERT(prp_index == NVME_MAX_PRP_LIST_ENTRIES + 1);
|
|
|
|
|
|
|
|
/* Buffer too large to be described in NVME_MAX_PRP_LIST_ENTRIES */
|
|
|
|
prp_list_prep(&tr, &req, &prp_index);
|
|
|
|
CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100000,
|
2019-11-01 18:16:43 +00:00
|
|
|
(NVME_MAX_PRP_LIST_ENTRIES + 2) * 0x1000, 0x1000) == -EFAULT);
|
2017-07-28 01:32:55 +00:00
|
|
|
|
|
|
|
/* Non-4K-aligned buffer too large to be described in NVME_MAX_PRP_LIST_ENTRIES */
|
|
|
|
prp_list_prep(&tr, &req, &prp_index);
|
|
|
|
CU_ASSERT(nvme_pcie_prp_list_append(&tr, &prp_index, (void *)0x100800,
|
2019-11-01 18:16:43 +00:00
|
|
|
(NVME_MAX_PRP_LIST_ENTRIES + 1) * 0x1000, 0x1000) == -EFAULT);
|
2017-07-28 01:32:55 +00:00
|
|
|
}
|
|
|
|
|
2019-10-31 14:42:48 +00:00
|
|
|
static void
|
|
|
|
test_nvme_pcie_hotplug_monitor(void)
|
|
|
|
{
|
2019-12-02 11:22:54 +00:00
|
|
|
struct nvme_pcie_ctrlr pctrlr = {};
|
2019-11-25 18:21:39 +00:00
|
|
|
struct spdk_uevent_entry entry = {};
|
|
|
|
struct nvme_driver driver;
|
2019-10-31 14:42:48 +00:00
|
|
|
pthread_mutexattr_t attr;
|
|
|
|
struct spdk_nvme_probe_ctx test_nvme_probe_ctx = {};
|
|
|
|
|
|
|
|
/* Initiate variables and ctrlr */
|
2019-11-25 18:21:39 +00:00
|
|
|
driver.initialized = true;
|
2020-06-01 06:12:06 +00:00
|
|
|
driver.hotplug_fd = 123;
|
2019-10-31 14:42:48 +00:00
|
|
|
CU_ASSERT(pthread_mutexattr_init(&attr) == 0);
|
2019-11-25 18:21:39 +00:00
|
|
|
CU_ASSERT(pthread_mutex_init(&driver.lock, &attr) == 0);
|
|
|
|
TAILQ_INIT(&driver.shared_attached_ctrlrs);
|
|
|
|
g_spdk_nvme_driver = &driver;
|
2019-10-31 14:42:48 +00:00
|
|
|
|
|
|
|
/* Case 1: SPDK_NVME_UEVENT_ADD/ NVME_VFIO */
|
2019-11-25 18:21:39 +00:00
|
|
|
entry.uevent.subsystem = SPDK_NVME_UEVENT_SUBSYSTEM_VFIO;
|
|
|
|
entry.uevent.action = SPDK_NVME_UEVENT_ADD;
|
|
|
|
snprintf(entry.uevent.traddr, sizeof(entry.uevent.traddr), "0000:05:00.0");
|
|
|
|
CU_ASSERT(STAILQ_EMPTY(&g_uevents));
|
|
|
|
STAILQ_INSERT_TAIL(&g_uevents, &entry, link);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
|
|
|
_nvme_pcie_hotplug_monitor(&test_nvme_probe_ctx);
|
|
|
|
|
2019-11-25 18:21:39 +00:00
|
|
|
CU_ASSERT(STAILQ_EMPTY(&g_uevents));
|
2019-10-31 14:42:48 +00:00
|
|
|
CU_ASSERT(g_device_is_enumerated == true);
|
|
|
|
g_device_is_enumerated = false;
|
|
|
|
|
|
|
|
/* Case 2: SPDK_NVME_UEVENT_ADD/ NVME_UIO */
|
2019-11-25 18:21:39 +00:00
|
|
|
entry.uevent.subsystem = SPDK_NVME_UEVENT_SUBSYSTEM_UIO;
|
|
|
|
entry.uevent.action = SPDK_NVME_UEVENT_ADD;
|
|
|
|
snprintf(entry.uevent.traddr, sizeof(entry.uevent.traddr), "0000:05:00.0");
|
|
|
|
CU_ASSERT(STAILQ_EMPTY(&g_uevents));
|
|
|
|
STAILQ_INSERT_TAIL(&g_uevents, &entry, link);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
|
|
|
_nvme_pcie_hotplug_monitor(&test_nvme_probe_ctx);
|
|
|
|
|
2019-11-25 18:21:39 +00:00
|
|
|
CU_ASSERT(STAILQ_EMPTY(&g_uevents));
|
2019-10-31 14:42:48 +00:00
|
|
|
CU_ASSERT(g_device_is_enumerated == true);
|
|
|
|
g_device_is_enumerated = false;
|
|
|
|
|
|
|
|
/* Case 3: SPDK_NVME_UEVENT_REMOVE/ NVME_UIO */
|
2019-11-25 18:21:39 +00:00
|
|
|
entry.uevent.subsystem = SPDK_NVME_UEVENT_SUBSYSTEM_UIO;
|
|
|
|
entry.uevent.action = SPDK_NVME_UEVENT_REMOVE;
|
|
|
|
snprintf(entry.uevent.traddr, sizeof(entry.uevent.traddr), "0000:05:00.0");
|
|
|
|
CU_ASSERT(STAILQ_EMPTY(&g_uevents));
|
|
|
|
STAILQ_INSERT_TAIL(&g_uevents, &entry, link);
|
2019-12-02 11:22:54 +00:00
|
|
|
|
2020-05-10 23:32:35 +00:00
|
|
|
MOCK_SET(nvme_get_ctrlr_by_trid_unsafe, &pctrlr.ctrlr);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
|
|
|
_nvme_pcie_hotplug_monitor(&test_nvme_probe_ctx);
|
|
|
|
|
2019-11-25 18:21:39 +00:00
|
|
|
CU_ASSERT(STAILQ_EMPTY(&g_uevents));
|
2019-12-02 11:22:54 +00:00
|
|
|
CU_ASSERT(pctrlr.ctrlr.is_failed == true);
|
|
|
|
pctrlr.ctrlr.is_failed = false;
|
2020-05-10 23:32:35 +00:00
|
|
|
MOCK_CLEAR(nvme_get_ctrlr_by_trid_unsafe);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
|
|
|
/* Case 4: SPDK_NVME_UEVENT_REMOVE/ NVME_VFIO */
|
2019-11-25 18:21:39 +00:00
|
|
|
entry.uevent.subsystem = SPDK_NVME_UEVENT_SUBSYSTEM_VFIO;
|
|
|
|
entry.uevent.action = SPDK_NVME_UEVENT_REMOVE;
|
|
|
|
snprintf(entry.uevent.traddr, sizeof(entry.uevent.traddr), "0000:05:00.0");
|
|
|
|
CU_ASSERT(STAILQ_EMPTY(&g_uevents));
|
|
|
|
STAILQ_INSERT_TAIL(&g_uevents, &entry, link);
|
2020-05-10 23:32:35 +00:00
|
|
|
MOCK_SET(nvme_get_ctrlr_by_trid_unsafe, &pctrlr.ctrlr);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
|
|
|
_nvme_pcie_hotplug_monitor(&test_nvme_probe_ctx);
|
|
|
|
|
2019-11-25 18:21:39 +00:00
|
|
|
CU_ASSERT(STAILQ_EMPTY(&g_uevents));
|
2019-12-02 11:22:54 +00:00
|
|
|
CU_ASSERT(pctrlr.ctrlr.is_failed == true);
|
|
|
|
pctrlr.ctrlr.is_failed = false;
|
2020-05-10 23:32:35 +00:00
|
|
|
MOCK_CLEAR(nvme_get_ctrlr_by_trid_unsafe);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
2019-11-25 18:21:39 +00:00
|
|
|
/* Case 5: Removed device detected in another process */
|
2019-12-02 11:22:54 +00:00
|
|
|
pctrlr.ctrlr.trid.trtype = SPDK_NVME_TRANSPORT_PCIE;
|
|
|
|
snprintf(pctrlr.ctrlr.trid.traddr, sizeof(pctrlr.ctrlr.trid.traddr), "0000:02:00.0");
|
|
|
|
pctrlr.ctrlr.remove_cb = NULL;
|
|
|
|
pctrlr.ctrlr.is_failed = false;
|
|
|
|
pctrlr.ctrlr.is_removed = false;
|
|
|
|
TAILQ_INSERT_TAIL(&g_spdk_nvme_driver->shared_attached_ctrlrs, &pctrlr.ctrlr, tailq);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
2019-11-25 18:21:39 +00:00
|
|
|
MOCK_SET(spdk_pci_device_is_removed, false);
|
|
|
|
|
2019-10-31 14:42:48 +00:00
|
|
|
_nvme_pcie_hotplug_monitor(&test_nvme_probe_ctx);
|
|
|
|
|
2019-12-02 11:22:54 +00:00
|
|
|
CU_ASSERT(pctrlr.ctrlr.is_failed == false);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
2019-11-25 18:21:39 +00:00
|
|
|
MOCK_SET(spdk_pci_device_is_removed, true);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
|
|
|
_nvme_pcie_hotplug_monitor(&test_nvme_probe_ctx);
|
|
|
|
|
2019-12-02 11:22:54 +00:00
|
|
|
CU_ASSERT(pctrlr.ctrlr.is_failed == true);
|
2019-10-31 14:42:48 +00:00
|
|
|
|
2019-11-25 18:21:39 +00:00
|
|
|
pthread_mutex_destroy(&driver.lock);
|
2019-10-31 14:42:48 +00:00
|
|
|
pthread_mutexattr_destroy(&attr);
|
2019-11-25 18:21:39 +00:00
|
|
|
g_spdk_nvme_driver = NULL;
|
2019-10-31 14:42:48 +00:00
|
|
|
}
|
|
|
|
|
2017-09-30 04:37:21 +00:00
|
|
|
static void test_shadow_doorbell_update(void)
|
|
|
|
{
|
|
|
|
bool ret;
|
|
|
|
|
|
|
|
/* nvme_pcie_qpair_need_event(uint16_t event_idx, uint16_t new_idx, uint16_t old) */
|
|
|
|
ret = nvme_pcie_qpair_need_event(10, 15, 14);
|
|
|
|
CU_ASSERT(ret == false);
|
|
|
|
|
|
|
|
ret = nvme_pcie_qpair_need_event(14, 15, 14);
|
|
|
|
CU_ASSERT(ret == true);
|
|
|
|
}
|
|
|
|
|
2019-11-22 22:14:25 +00:00
|
|
|
static void
|
|
|
|
test_build_contig_hw_sgl_request(void)
|
|
|
|
{
|
|
|
|
struct spdk_nvme_qpair qpair = {};
|
|
|
|
struct nvme_request req = {};
|
|
|
|
struct nvme_tracker tr = {};
|
|
|
|
int rc;
|
|
|
|
|
|
|
|
/* Test 1: Payload covered by a single mapping */
|
|
|
|
req.payload_size = 100;
|
|
|
|
req.payload = NVME_PAYLOAD_CONTIG(0, 0);
|
|
|
|
g_vtophys_size = 100;
|
|
|
|
MOCK_SET(spdk_vtophys, 0xDEADBEEF);
|
|
|
|
|
2020-03-19 05:04:05 +00:00
|
|
|
rc = nvme_pcie_qpair_build_contig_hw_sgl_request(&qpair, &req, &tr, 0);
|
2019-11-22 22:14:25 +00:00
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.type == SPDK_NVME_SGL_TYPE_DATA_BLOCK);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == 0xDEADBEEF);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.length == 100);
|
|
|
|
|
|
|
|
MOCK_CLEAR(spdk_vtophys);
|
|
|
|
g_vtophys_size = 0;
|
|
|
|
memset(&qpair, 0, sizeof(qpair));
|
|
|
|
memset(&req, 0, sizeof(req));
|
|
|
|
memset(&tr, 0, sizeof(tr));
|
|
|
|
|
|
|
|
/* Test 2: Payload covered by a single mapping, but request is at an offset */
|
|
|
|
req.payload_size = 100;
|
|
|
|
req.payload_offset = 50;
|
|
|
|
req.payload = NVME_PAYLOAD_CONTIG(0, 0);
|
|
|
|
g_vtophys_size = 1000;
|
|
|
|
MOCK_SET(spdk_vtophys, 0xDEADBEEF);
|
|
|
|
|
2020-03-19 05:04:05 +00:00
|
|
|
rc = nvme_pcie_qpair_build_contig_hw_sgl_request(&qpair, &req, &tr, 0);
|
2019-11-22 22:14:25 +00:00
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.type == SPDK_NVME_SGL_TYPE_DATA_BLOCK);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == 0xDEADBEEF);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.length == 100);
|
|
|
|
|
|
|
|
MOCK_CLEAR(spdk_vtophys);
|
|
|
|
g_vtophys_size = 0;
|
|
|
|
memset(&qpair, 0, sizeof(qpair));
|
|
|
|
memset(&req, 0, sizeof(req));
|
|
|
|
memset(&tr, 0, sizeof(tr));
|
|
|
|
|
|
|
|
/* Test 3: Payload spans two mappings */
|
|
|
|
req.payload_size = 100;
|
|
|
|
req.payload = NVME_PAYLOAD_CONTIG(0, 0);
|
|
|
|
g_vtophys_size = 60;
|
|
|
|
tr.prp_sgl_bus_addr = 0xFF0FF;
|
|
|
|
MOCK_SET(spdk_vtophys, 0xDEADBEEF);
|
|
|
|
|
2020-03-19 05:04:05 +00:00
|
|
|
rc = nvme_pcie_qpair_build_contig_hw_sgl_request(&qpair, &req, &tr, 0);
|
2019-11-22 22:14:25 +00:00
|
|
|
CU_ASSERT(rc == 0);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.type == SPDK_NVME_SGL_TYPE_LAST_SEGMENT);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.address == tr.prp_sgl_bus_addr);
|
|
|
|
CU_ASSERT(req.cmd.dptr.sgl1.unkeyed.length == 2 * sizeof(struct spdk_nvme_sgl_descriptor));
|
|
|
|
CU_ASSERT(tr.u.sgl[0].unkeyed.type == SPDK_NVME_SGL_TYPE_DATA_BLOCK);
|
2020-06-01 02:12:23 +00:00
|
|
|
CU_ASSERT(tr.u.sgl[0].unkeyed.length == 60);
|
|
|
|
CU_ASSERT(tr.u.sgl[0].address == 0xDEADBEEF);
|
2019-11-22 22:14:25 +00:00
|
|
|
CU_ASSERT(tr.u.sgl[1].unkeyed.type == SPDK_NVME_SGL_TYPE_DATA_BLOCK);
|
2020-06-01 02:12:23 +00:00
|
|
|
CU_ASSERT(tr.u.sgl[1].unkeyed.length == 40);
|
|
|
|
CU_ASSERT(tr.u.sgl[1].address == 0xDEADBEEF);
|
2019-11-22 22:14:25 +00:00
|
|
|
|
|
|
|
MOCK_CLEAR(spdk_vtophys);
|
|
|
|
g_vtophys_size = 0;
|
|
|
|
memset(&qpair, 0, sizeof(qpair));
|
|
|
|
memset(&req, 0, sizeof(req));
|
|
|
|
memset(&tr, 0, sizeof(tr));
|
|
|
|
}
|
|
|
|
|
2017-01-05 23:12:54 +00:00
|
|
|
int main(int argc, char **argv)
|
|
|
|
{
|
|
|
|
CU_pSuite suite = NULL;
|
|
|
|
unsigned int num_failures;
|
|
|
|
|
2020-03-11 17:59:24 +00:00
|
|
|
CU_set_error_action(CUEA_ABORT);
|
|
|
|
CU_initialize_registry();
|
2017-01-05 23:12:54 +00:00
|
|
|
|
|
|
|
suite = CU_add_suite("nvme_pcie", NULL, NULL);
|
2020-03-11 19:15:39 +00:00
|
|
|
CU_ADD_TEST(suite, test_prp_list_append);
|
|
|
|
CU_ADD_TEST(suite, test_nvme_pcie_hotplug_monitor);
|
|
|
|
CU_ADD_TEST(suite, test_shadow_doorbell_update);
|
|
|
|
CU_ADD_TEST(suite, test_build_contig_hw_sgl_request);
|
2017-01-05 23:12:54 +00:00
|
|
|
|
|
|
|
CU_basic_set_mode(CU_BRM_VERBOSE);
|
|
|
|
CU_basic_run_tests();
|
|
|
|
num_failures = CU_get_number_of_failures();
|
|
|
|
CU_cleanup_registry();
|
|
|
|
return num_failures;
|
|
|
|
}
|